7.4 NMOS Transistor

The example in Fig. 7.22 shows a NMOS transistor in $0.18 \mu m$ technology. Two regions of field oxide isolate the bottom silicon bulk from the poly-silicon. The gate is formed in the center of the depicted structure between the field oxides under the crossing poly-silicon. The gate-oxide which isolates the poly-silicon from the silicon at the gate area is $5 nm$ thick and not visible in the figure. The size of the gate is given by the width of the poly-silicon and the distance between the field oxides ( $0.18 \mu m \times 0.18 \mu m$). A $30 nm$ thin oxide layer covers the entire structure. The structural edges of the device can be seen in Fig. 7.21.

Devices with high ratios between local feature sizes pose a challenge to most existing meshing methods. The difficulty lies in the anisotropic grading of the mesh density. Isotropic grading results in a mesh with a too large number of elements in three dimensions. The above described device exhibits such a geometrical anisotropy which was managed through a specific technique for the generation of the internal mesh points. As can be observed in Fig. 7.23 the mesh possesses long and thin elements to resolve the thin layer. The mesh points were generated at cross-sections of the structure. The tetrahedralization performed by the modified advancing front algorithm produced the desired anisotropic elements. As can be seen from the left side wall in Fig. 7.23 the mesh is fully three-dimensional and could not have been generated by extruding a two-dimensional mesh as for example through a layer-based product method which was described in Section 4.2.1). However, the resulting mesh elements are not completely ideal, because their anisotropy is one-dimensional. Flat prismatic elements may be preferred to resolve the thin layer.

Figure 7.21: Structural edges.

Figure 7.22: NMOS Transistor with a thin oxide layer.

Figure 7.23: Boron implantation profile, mesh with 134374 elements.