6. Summary and Conclusions

TUNNELING EFFECTS in semiconductor devices were investigated and simulated with MINIMOS-NT. Starting with an introduction to CMOS technology and semiconductor device simulation, a hierarchy of tunneling models was outlined. Three main properties were identified to influence the tunneling process: The carrier energy distribution function, the transmission coefficient, and the presence of traps in the dielectric layer.

The energetic distribution of carriers was investigated using different approximations, such as the frequently applied FERMI-DIRAC or MAXWELL-BOLTZMANN statistics. However, these approximations are only valid near equilibrium. Comparisons with the results from Monte Carlo simulations showed that in turned-on devices the distribution function strongly deviates from the ideal shape. Some non-MAXWELLian models were reviewed and it was found that a model which is based on the solution variables of a six-moments transport model accurately reproduces the Monte Carlo results.

The quantum-mechanical transmission coefficient can be computed from the solution of the stationary SCHRÖDINGER equation. Several approximations and analytical formulae were outlined. For a single-layer dielectric the analytical WKB approximation or GUNDLACH's formula can be used. For arbitrary-shaped energy barriers the numerical WKB, the transfer-matrix, or the quantum transmitting boundary method can be applied. It was found that the transfer-matrix method is prone to numerical problems due to the repeated matrix multiplications. The quantum transmitting boundary method turned out to be more robust.

Defects in the dielectric layer give rise to trap-assisted tunneling which leads to an additional tunneling current at low bias. After reviewing several models from the literature a recently presented inelastic trap-assisted tunneling model was adapted to avoid the numerical calculation of the overlap integral in the dielectric layer. This yielded a fully analytical model which was further developed to include transient trap charging and discharging effects.

All methods were implemented into the general-purpose device simulator MINIMOS-NT. The implementation was shortly described. Furthermore, a multi-dimensional SCHRÖDINGER solver was implemented to calculate the transmission coefficient and the energy eigenvalues of arbitrary energy barriers. This solver was designed in such a way that both open and closed boundary conditions can be applied on the same band diagram.

Several examples were studied where a general distinction between tunneling in MOS transistors, where it is a parasitic effect, and tunneling in non-volatile memory devices, where it is crucial for the device functionality, was made. Tunneling in MOS transistors was investigated, where special attention was paid on the investigation of the different tunneling paths from the gate to the channel and from the gate to the source and drain extension regions.

Furthermore, the importance of the carrier distribution functions for modeling of gate leakage in turned-on devices was shown. If a heated MAXWELLian approximation was used for the description of hot-carrier tunneling, the gate current density was heavily overestimated. This effect was found to be especially pronounced for devices with short gate lengths.

In future CMOS devices the use of alternative dielectric materials instead of SiO$_2$ will make the reduction of the effective oxide thickness possible. Several candidate materials were studied and it was found that they show a pronounced correlation between the barrier height and the permittivity. This makes optimization necessary to find the optimum layer composition. Furthermore, the investigation of a MOS capacitor with a ZrO$_2$ dielectric showed that the strong defect density makes the use of trap-assisted tunneling models a sine qua non for these materials.

In addition to MOS transistors non-volatile memory devices were studied. A general overview of non-volatile memory technology was followed by an investigation of three selected device structures: devices where the floating gate contact is replaced by a layer of trap-rich dielectric, multi-barrier tunneling devices, and devices which are based on crested barriers. Especially the multi-barrier tunneling devices allow an extremely high $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio. The trap-rich dielectric devices, on the other hand, are easier to fabricate and have a smaller footprint. Devices which are based on crested barriers allow to tune the on- and off-current density independently. However, the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$-ratio heavily depends on the thicknesses of the dielectric layers and simulation is necessary to find the optimum values. The investigated non-volatile memory applications are expected to show high performance, however, the bad quality of the interface between the dielectric layers may offset the advantage in the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$-ratio.

The implementation of these direct and trap-assisted tunneling models allows the simulation and analysis of semiconductor devices where tunneling is either a parasitic effect or deliberately used as a part of the device functionality. Future work will concentrate on the coupling of the developed multi-dimensional SCHRÖDINGER solver to MINIMOS-NT to simulate quantization effects in MOSFET inversion layers and for the characterization of alternative dielectric materials. The numerical methods to calculate tunneling from quasi-bound states will be investigated in more detail. Finally, the developed tunneling models will be applied to the simulation of gate dielectric reliability issues.

A. Gehring: Simulation of Tunneling in Semiconductor Devices