5.2.2.3 Non-Volatile Memory Devices Based on Crested Barriers

As shown in Section 5.2.2.2, one of the most important figures of merit of a non-volatile memory cell is its $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$-ratio: A high on-current leads to low programming and erasing times, and a low off-current increases the retention time of the device. This ratio can be increased if, for a given device, the tunneling current in the on-state (the charging/discharging current) is increased or, in the off-state (during the retention time), decreased. With a single-layer dielectric it is not possible to tune on- and off-current independently. However, if the tunnel dielectric is replaced by a dielectric stack of varying barrier height as shown in Fig. 5.38, it becomes possible. In this figure the device structure and the conduction band edge in the on- and off-state are shown. The device consists of a standard EEPROM structure, where the tunnel dielectric is composed of three layers. The middle layer has a higher energy barrier than the inner and outer layers. The flat-band case is indicated by the dotted lines.

In the on-state a high voltage is applied on the top contact. The middle energy barrier is strongly reduced and gives rise to a high tunneling current. If the dielectric would consist of a single layer, the peak of the energy barrier would not be reduced. Thus, the on-current is much higher for the layered dielectric. In the off-state a low negative voltage -- due to charge stored on the memory node -- is applied. The middle barrier is only slightly suppressed and blocks tunneling. The off-current is only slightly lower than for a single-layer dielectric. This behavior results in a high $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio. A high suppression of the middle barrier in the on-state requires a low permittivity of the outer layers so that the potential drop in the outer layers is high [261]. This device design was first proposed by CAPASSO et al. in 1988 [298] based on AlGaAs-GaAs devices and later used by several authors [299,300], where it became popular as crested-barrier memory or VARIOT (varying oxide thickness device).

Figure 5.38: Device structure and operating principle of a non-volatile memory based on crested barriers.

The gate current density of the device depicted in Fig. 5.38 is shown as a function of the gate bias in the left part of Fig. 5.39. A stack thickness of 5nm was chosen. Since the middle layers must have a high band gap, only few material combinations are possible. For the simulations middle layers of Al$_2$O$_3$ and SiO$_2$ have been chosen, with outer layers of Y$_2$O$_3$, Si$_3$N$_4$, and ZrO$_2$. For comparison full SiO$_2$ and Si$_3$N$_4$ stacks have also been simulated (the dotted and dash-dotted lines). While Y$_2$O$_3$ shows a very high off-current, stacks with outer layers of Si$_3$N$_4$ or ZrO$_2$ and Al$_2$O$_3$ as middle layer show good ratios between the on-state (positive gate bias) current density and the off-state (negative gate bias) current density.

The important figure of merit, however, is the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$-ratio. In the right part of Fig. 5.39 the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$-ratio is shown for Si$_3$N$_4$ and ZrO$_2$ stacks with SiO$_2$ and Al$_2$O$_3$ middle layers as a function of the thickness of the middle layer. Also shown is the ratio for a layer of SiO$_2$ and Si$_3$N$_4$ alone. It is obvious that the ratio strongly depends on the thickness of the middle layer, and both minima and maxima can be observed. Only outer layers of Si$_3$N$_4$ lead to a significantly increased performance as compared to full layers of SiO$_2$ or Si$_3$N$_4$. A middle layer thickness around 1-2nm for the assumed 6nm stack gives optimum performance.

Figure 5.39: Gate current density as a function of the gate bias for different materials of the middle layer, compared to full SiO$_2$ and Si$_3$N$_4$ layers (left). Ratio between the on-current and the off-current as a function of the middle layer thickness for different materials of the outer layers (Si$_3$N$_4$ and ZrO$_2$) and middle layers (Al$_2$O$_3$ and SiO$_2$), compared to the resulting current density using full layers of SiO$_2$ and Si$_3$N$_4$ (right).

A. Gehring: Simulation of Tunneling in Semiconductor Devices