As shown in Section 5.2.2.2, one of the most important figures of merit of a
non-volatile memory cell is its
-ratio: A high on-current leads to low
programming and erasing times, and a low off-current increases the retention
time of the device. This ratio can be increased if, for a given device, the
tunneling current in the on-state (the charging/discharging current) is
increased or, in the off-state (during the retention time), decreased. With a
single-layer dielectric it is not possible to tune on- and off-current
independently. However, if the tunnel dielectric is replaced by a dielectric
stack of varying barrier height as shown in Fig. 5.38, it
becomes possible. In this figure the device structure and the conduction band
edge in the on- and off-state are shown. The device consists of a standard
EEPROM structure, where the tunnel dielectric is composed of three layers. The
middle layer has a higher energy barrier than the inner and outer layers. The
flat-band case is indicated by the dotted lines.
In the on-state a high voltage is applied on the top contact. The middle
energy barrier is strongly reduced and gives rise to a high tunneling current.
If the dielectric would consist of a single layer, the peak of the energy
barrier would not be reduced. Thus, the on-current is much higher for the
layered dielectric. In the off-state a low negative voltage -- due to
charge stored on the memory node -- is applied. The middle barrier is only
slightly suppressed and blocks tunneling. The off-current is only slightly
lower than for a single-layer dielectric. This behavior results in a high
ratio. A high suppression of the middle barrier in the on-state
requires a low permittivity of the outer layers so that the potential drop in
the outer layers is high [261]. This device design was first
proposed by CAPASSO et al. in 1988 [298] based on AlGaAs-GaAs devices
and later used by several authors [299,300], where it
became popular as crested-barrier memory or VARIOT (varying oxide
thickness device).
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The gate current density of the device depicted in Fig. 5.38
is shown as a function of the gate bias in the left part of
Fig. 5.39. A stack thickness of 5nm was chosen. Since the
middle layers must have a high band gap, only few material combinations are
possible. For the simulations middle layers of AlO
and SiO
have been
chosen, with outer layers of Y
O
, Si
N
, and ZrO
. For comparison full SiO
and Si
N
stacks have also been simulated (the dotted and dash-dotted lines).
While Y
O
shows a very high off-current, stacks with outer layers of Si
N
or ZrO
and Al
O
as middle layer show good ratios between the on-state
(positive gate bias) current density and the off-state (negative gate bias)
current density.
The important figure of merit, however, is the
-ratio. In the right
part of Fig. 5.39 the
-ratio is shown for Si
N
and
ZrO
stacks with SiO
and Al
O
middle layers as a function of the
thickness of the middle layer. Also shown is the ratio for a layer of SiO
and Si
N
alone. It is obvious that the ratio strongly depends on the
thickness of the middle layer, and both minima and maxima can be observed.
Only outer layers of Si
N
lead to a significantly increased performance as
compared to full layers of SiO
or Si
N
. A middle layer thickness around
1-2nm for the assumed 6nm stack gives optimum performance.
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A. Gehring: Simulation of Tunneling in Semiconductor Devices