5.2.2 Alternative Non-Volatile Memory Devices

Strong efforts are undertaken to improve the standard floating-gate EEPROM cell shown in Fig. 5.25 in terms of integration density, endurance, reliability, program time, erase time, and retention time. Some of these approaches are depicted schematically in Fig. 5.29 and Fig. 5.30. EEPROM devices with a tunnel window near the drain contact have been introduced to reduce the charge loss from the floating gate and thus reach higher retention time. However, due to the small area of the tunnel window high voltages have to be used at the drain contact which again reduces cell reliability.

Recently, CAYWOOD et al. proposed a device structure where non-selected cells are isolated from the drain and source contacts by two additional side gates [280]. In this device electrons tunnel from the inverted channel to the floating gate. The large area reduces programming and erasing time. Furthermore, the capacitive coupling between the control gate and the floating gate is higher than in the standard EEPROM cell which allows to use lower programming and erasing voltages. No drain-source bias is applied for charging, thus the power consumption is low and the injected electrons are less likely to cause degradation of the dielectric. The control gate functions as a select transistor which isolates unselected cells from the high voltages at the shared source and drain contacts during read and write access of neighboring cells.

Figure 5.29: Alternative NVM structures: EEPROM with tunnel window (left), CAYWOOD memory device (right).

In contrast to the reduction of the cell footprint, integration density can also be increased by storing more than one bit on a standard EEPROM cell. This can be achieved by tailoring the programming and erasing pulses in such a way that the threshold voltage falls into one of 4, 8, or 16 voltage ranges. The different threshold voltages can be distinguished by the sensing circuits, resulting in two, three, or four bits which can be stored in the cell. However, charge loss must be extremely low over time and the threshold voltages have to be detected very precisely.

Single-poly devices as shown in the left part of Fig. 5.30 have been proposed to integrate NVM devices in standard CMOS logic processes, thus enabling an embedded memory. The control gate lies next to the floating gate and capacitive coupling is achieved by a layer of highly doped silicon. While such devices can readily be integrated into existing CMOS process flows, they come at the cost of a large footprint.

A different approach to store more than one bit in a single memory cell is to split the floating gate into two separate segments. If a non-uniform doping in the source and drain side of the channel is used, different amounts of charge can be stored in each floating gate. Such device structures are either achieved using separate metallic floating gates like the contacts FG1 and FG2 in the right part of Fig. 5.30 [182], or using a layer of trap-rich dielectric [281].

Figure 5.30: Alternative NVM structures: Single-poly EEPROM (left), split-gate EEPROM (right).

In the following sections three of the most promising alternative EEPROM devices will be studied in detail. These are

• Quantum dot and trap-rich dielectric based devices. In these devices, charging and discharging is achieved by tunneling of electrons to and from localized trapping centers in the dielectric.

• Multi-barrier tunneling devices consist of a floating gate -- or memory node -- which is separated from the control gate by several thin dielectric layers. By the use of a side gate, the tunneling current through these barriers can be controlled selectively. In contrast to EEPROMs the tunneling current flows from the floating gate to the control gate and not to the channel. Extremely high $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratios can be achieved because the tunneling current is controlled by a separate side gate contact.

• Devices where the tunnel dielectric consists of stacked dielectrics which are engineered in such a way that they block tunneling in the off-state, but allow strong tunneling in the on-state.

Subsections

• 5.2.2.1 Non-Volatile Memory Devices Based on Trap-Rich Dielectrics
• 5.2.2.2 Multi-Barrier Tunneling Devices
• 5.2.2.3 Non-Volatile Memory Devices Based on Crested Barriers

A. Gehring: Simulation of Tunneling in Semiconductor Devices