The physical thickness of the dielectric has the largest impact on the gate
current density, as shown in Fig. 5.5. Increasing the gate
dielectric thickness by 0.4nm leads to a decrease of all tunneling current
components by several orders of magnitude.
Figure 5.5:
Electron (left) and hole (right) current density
in an nMOS (top) and a pMOS (bottom) with different thickness of the
dielectric layer. Gate polysilicon doping is 5e20 cm-3, substrate doping is
5e18 cm-3.