5.1.3 Source and Drain Extension Tunneling

In the following examples the same devices as in Section 5.1.1 are investigated, but this time only the tunneling current in the source and drain extension areas (n-n or p-p) is taken into account. Since the barrier height, carrier mass, and dielectric thickness shows the same impact on the gate current density as for the case of channel tunneling, the corresponding figures are omitted.

Subsections

• 5.1.3.1 Effect of the Polysilicon Gate Doping on the Source and Drain Extension Tunneling
• 5.1.3.2 Effect of the Substrate Doping on the Source and Drain Extension Tunneling
• 5.1.3.3 Effect of the Dielectric Permittivity on the Source and Drain Extension Tunneling
• 5.1.3.4 Effect of the Lattice Temperature on the Source and Drain Extension Tunneling

A. Gehring: Simulation of Tunneling in Semiconductor Devices