The well established techniques to study the interface states are: the
comparative low-frequency (quasi-static) and high-frequency (HF) 
-
technique [48], the small-signal admittance (conductance and
capacitance) techniques ([331]) and the deep-level transient
spectroscopy techniques (DLTS) [264]. These methods are originally
proposed for (and restricted to) large-area MOS capacitors. Due to large
parasitic capacitances compared to the active capacitance and the very small
signal produced, they cannot be applied to small MOSFETs. An exhaustive review
of these techniques can be found in [331], comparative studies in
e.g. [508][332], and some recent improvements of these methods
and novel methods in e.g. [446][388][240][218][149][112][64][63].
Among the experiments to measure the charge-pumping current we note other
techniques to study the interface states
:
:
Interface traps increase the slope of the subthreshold characteristics
with respect to the characteristics of
the same device with no traps. From the shift of the subthreshold slope
one can extract the trap density at about the middle of the upper part of
the band gap. Any nonuniformity along the interface does not permit an
accurate application of this method (two-dimensional effects in short
channel devices and nonuniform distributions of interface traps and fixed
oxide charge). Therefore, this method is applicable on long-channel
devices only. In addition, a uniformly doped bulk should be assumed.
Moreover, the surface-potential fluctuations have an influence in this
technique [488][487]. Recently, it has been proposed to
scan the upper part of the band gap by this method [282].
However, the same serious limitations noted above remain.
:
It has been postulated for a long time that the random transitions of
the free carriers into and from the interface states and oxide traps
and/or the mobility fluctuations produce the 
noise in MOSFETs
(cf. [483][383][193]). A correlation between the
noise and the interface-state/oxide-trap density found by several
researchers supports the first origin [253][137]. The
nature of these transitions is, however, not clear: tunneling, thermionic
emission or a combination of both processes seem to be an
explanation [411][381][251][241][137]. It has
been recently determined that the shape of the noise power spectral
density on MOSFETs results from a superposition of the random switching
signals (RTS discussed below) of many active
traps [483][381][251][155].
According to the present understanding of the RTS, the switching
originates from the change in the number of free carriers, due to
trapping/detrapping and the change in the local channel mobility due to
an electrostatic influence of the trapped charge depending on the type of
trap [483][437][411][381]. It can be shown that the
low-frequency noise power spectral density is directly related to the
interface-trap density actually scanned (
few 
away from the
Fermi level at the interface), but the coefficient of the proportionality
depends on the physical process involved at the transition. This
proportionality can be exploited to extract the interface-trap density
distribution in the energy space [228]. In
very small devices the noise spectrum deviates from the shape. It
becomes a superposition of the switching (RTS) spectra of a few traps
active at the given gate bias [483][36]. By analyzing this
spectrum the properties of the single traps can be studied.
:
It is probably the most promising method to study interface traps. RTS
yields information on the single-electron capture and emission into and
from a single trap by monitoring in time the small quantized switching
transients in the channel conductivity [483][425][424][411][381][251][220][36]
. In some cases, very large transient changes are
observed [350]. In very small devices the total number of
interface traps can be very low. For channel length 
,
channel width 
and interface-trap density
(typical for careful
processing today), there are only
traps in the device. We can scan the traps separately, by moving the Fermi level
position at the interface with changing the gate bias. The RTS technique
has been applied to study the traps generated in hot-carrier
stress [436][255][121][120][36] as well. The
topic currently discussed in the literature is modeling the amplitude of
the change in the channel conductivity due to the single capture and
emission events [483][437][411][389][383][350][220][155].
:
It has been adapted to short channel MOSFETs in [178]. Like
in the classical input-conductance technique on MOS
capacitors [331], the gate conductance and capacitance are
measured versus frequency for different gate voltages on MOSFETs. The
source, drain and bulk of device under investigation are connected
together. For the gate bias in the depletion region the interface states
communicate with the valence band (assuming an 
-channel MOSFET), which
enables one to analyze the lower part of the band gap, as in the classical
conductance method. For the gate bias in weak and strong inversion, the
interface states communicate with the conduction band. If the channel
length is sufficiently small for the time constant of the channel to
become negligible, the interface traps can be simply characterized in the
upper part of the band gap in the same way as for the lower part. The
channel time constant and its influence in the proposed technique have
been carefully considered in [178]. Parasitic capacitances are
eliminated in this technique by measuring them with the split -
method [256]. From the calculated trap conductance one can
extract 
, 
in the upper part
of the band gap, 
in the lower part of the band gap and
the standard deviation of the surface-potential fluctuations, as in the
classical conductance method, but all on the same small MOSFET. To obtain
the energy distributions, the relation between the surface potential and
the gate bias ought to be known for the device under
consideration [331].
:
The method is essentially a variation of the large-signal
charge-pumping method, but instead of measuring the DC component
of the currents, one monitors, in time, the substrate 
and the
source/drain 
switching currents during the course of the
experiment. In this way, the emission and
capture processes at the rising edge can be separated from those at the
falling edge of the gate pulse, while they are normally subtracted when
measuring the DC component. Consequently, the mean values of the capture
cross-sections for electrons and holes can be extracted independently,
by applying the triangular gate waveform. The terminal switching currents contain
the dominant displacement component, and the components due to the
electron and hole emission and capture currents from the interface
states. We will qualitatively consider the switching currents in
Appendix D. In [115], the authors have
developed an analytical (one-dimensional) model for the terminal currents
and as a function of the gate-bias slope
, interface emission and capture currents, the gate-channel
and gate-bulk 
capacitances, assuming an instantaneous
response of the majority and minority carriers. Therefore, the technique
is restricted to short channel devices. and as function
of 
are measured by the standard HF split -
technique [256] (at high frequency all traps become inactive,
but the channel charge still can follow the gate bias). Obtaining
and the dominant displacement component can be calculated and
eliminated from the switching terminal currents, allowing an extraction of
the emission and capture current components. To relate these components
to interface traps, a model for the interface emission and capture
processes is applied based on [435][233][232][154].
:
In [177] the authors have derived a simple direct relationship
between the transfer admittance
and the interface-trap
admittance (
), assuming an instantaneous response
of the minority carriers. Due to the last prerequisite the technique (in
its simple form) is restricted to MOSFETs with the channel length
sufficiently small so that the channel-charge time constant (in the weak
inversion) is much smaller than the time constant of the interface traps.
It has been shown in [177] that 
is proportional to the
imaginary part of the transimpedance 
. For the weak
inversion the expression reduces to a simple form
. After measuring the
quantity 
versus frequency at different gate biases, the
interface-trap parameters
and in the upper part of the band
gap and the surface-potential fluctuations can be extracted in
the standard way (Section 5 in [331]). Measuring the
transadmittance instead of the input admittance has the advantage that the
former signal is larger (a direct relationship between both admittances
is derived in [177]). This technique has been applied on the
depletion-mode SOI devices in [176].
is independent of the trap properties because the
traps are inactive at high frequencies. Subtracting both admittances from
each other the depletion and the inversion-layer capacitances can be
eliminated and we arrive at
.
has to be
obtained in order to transform the gate-bias axis to the energy axis.
:
The conventional DLTS technique based on monitoring the gate-capacitance
transients ([264]) has been adapted to MOSFETs in [498],
thus enabling that both the lower (majorities) and the upper (minorities)
part of the band gap can be analyzed in the same device. In [498]
the standard DLTS has been exploited, a procedure which consists of
measuring the spectroscopic signal versus the ambient temperature, to
extract the interface and bulk trap properties. In order to measure
transients in the gate capacitance in the deep-depletion very large gate
areas are required, otherwise the signal cannot be resolved. Therefore,
the method proposed in [498] is inapplicable to small size MOSFETs.
Instead of monitoring the gate capacitance, the authors of [71]
constructed the spectroscopic signal from transients in the drain
current, which can be easily measured for very small devices. In fact,
they measured the AC channel conductance in the linear region. The change
in the channel conductance between two fixed times which determine the
known DLTS window, is measured versus the ambient temperature. This
procedure, derived in [498] for SOI devices, has been applied later
to study both interface and bulk traps in recrystallized-Si
film [268] and SIMOX [304] SOI devices. In [304]
the current DLTS is introduced. In this experimental method, the drain
current is monitored. The current DLTS has also been adapted to study the
bulk traps (traps at the grain boundaries) in the fully depleted poly-Si
thin-film FETs in [19] (when trap concentration is higher than
dopant concentration). An alternative is to observe transients in terminal
voltages at constant current, as employed in [421] in studying
traps in GaAs MESFETs.
:
For nonzero drain-bulk bias non-equilibrium
conditions occur in the gate/drain overlap region due to nonzero
lateral electric field. For forward drain-bulk bias the lateral field
tends to increase the carrier concentrations, while for reverse bias
the carriers should be removed from the depletion region. The
conditions at the interface are affected by the gate bias too. Assuming
reverse drain-bulk bias and negative gate bias deep-depletion occurs
and the emission of electron and holes, predominantly from the midgap
traps, produce a generation current. The generated holes flow to the
bulk, whereas the generated electrons produce a positive drain current.
This leakage current contains information on the product
for the midgap traps in the depleted
region. Since the pioneering papers [156][133] the gated-diode
leakage has been thoroughly investigated in literature and applied to
evaluate the quality of the MOS interface (e.g. [207]).
However, a rigorous analysis in [372] (see [344] also)
has shown that the real situation is much more complicated than that
assumed in [156][133], questioning the practical accuracy of the
method. A short review of the leakage measurements is presented in
Section 3.5.2, while discussing the extraction of
the spatial trap distribution in the gate/drain overlap area.