- 1
-
G. E. Moore, ``Cramming more components onto integrated circuits,'' Electronics, pp. 114-117, April 1965.
- 2
-
R. Bauer, Numerische Berechnung von Kapazitäten in dreidimensionalen
Verdrahtungsstrukturen.
Dissertation, Technische Universität Wien, 1994.
http://www.iue.tuwien.ac.at/phd/bauer.
- 3
-
R. Sabelka, Dreidimensionale Finite Elemente Simulation von
Verdrahtungsstrukturen Integrierten Schaltungen.
Dissertation, Technische Universität Wien, 2001.
http://www.iue.tuwien.ac.at/phd/sabelka.
- 4
-
E. Chiprout, ``Hierachical interconnect modeling,'' in in
Proc.Intl.Electron Devices Meeting, pp. 125-128, 1997.
- 5
-
M. Bächtold, S. Taschini, J. G. Korvink, and H. Baltes, ``Automated
extraction of capacitances and electrostatic forces in MEMS and ULSI
interconnects from mask layout,'' in Proc. Intl.Electron Devices
Meeting, pp. 129-132, 1997.
- 6
-
G. Schumicki and P. Seegebrecht, Prozeßtechnologie.
Springer, 1991.
- 7
-
A. Furuyaz, M. Tagamiz, K. Shibaz, K. Kikutaz, and Y. Hayashi, ``Evaluation of
CVD/PVD multilayered seed for electrochemical deposition of Cu
Damascene interconnects,'' IEEE Trans.Electron Devices, vol. 49,
no. 5, pp. 733-738, 2002.
- 8
-
J. R. Black, ``Electromigration--A brief study and some recent results,''
IEEE Trans.Electron Devices, vol. ED-16, no. 3, pp. 338-347, 1969.
- 9
-
W. Wu, J. Yuan, S. Kang, and A. Oates, ``Electromigration subjected to Joule
heating under pulsed DC stress,'' Solid-State Electron., vol. 45,
no. 12, pp. 2051-2056, 2001.
- 10
-
Z. Li, G. Wu, Y. Wang, Z. Li, and Y. Sun, ``Numerical calculation of
electromigration under pulse current with Joule heating,'' IEEE
Trans.Electron Devices, vol. 46, no. 1, pp. 70-77, 1999.
- 11
-
X. Gui, J. Haslett, S. Dew, and M. Brett, ``Simulation of temperature cycling
effects on electromigration behavior under pulsed current stress,'' IEEE
Trans.Electron Devices, vol. 45, no. 2, pp. 380-386, 1998.
- 12
-
W. Wu and J. Yuan, ``Copper electromigration modeling including barrier layer
effect,'' Solid-State Electron., vol. 45, no. 12, pp. 2011-2016, 2001.
- 13
-
A. Salman, R. Gauthier, W. Stadler, K. Esmark, M. Muhammad, C. Putnam, and
D. Ioannou, ``NMOSFET ESD self-protection strategy and underlying failure
mechanism in advanced 0.13
m CMOS technology,'' Transactions on
Device and Materials Reliability, vol. 2, no. 1, pp. 2-8, 2002.
- 14
-
Y. Nishi and J. W. McPherson, ``Impact of new materials, changes in physics and
continued ULSI scaling on failure mechanisms and analysis,'' in Proc.
7th Intl. Symposium on the the Physical and Failure Analysis of Integrated
Circuits (IPFA), IEEE, Singapore, pp. 1-8, 1999.
- 15
-
M. Moussavi, ``Advanced interconnect schemes towards 0.1
m,'' in Proc. Electron Device Meeting, pp. 611-614, 1998.
- 16
-
K. J. Taylor, S. P. Jeng, M. Eissa, J. Gaynor, and N. Nguyen, ``Polymers for
high performance interconnects,'' in Proc. Conference Materials for
Advanced metallization, pp. 59-63, 1997.
- 17
-
R. Liu, C.-S. Pai, and E. Martinez, ``Interconnect technology trend for
microelectronics,'' Solid-State Electron., vol. 43, no. 6,
pp. 1003-1009, 1999.
- 18
-
R. H. Havemann and J. A. Hutchby, ``High-performance interconnects: An
integration overview,'' Proc.IEEE, vol. 89, no. 5, pp. 586-601, 2001.
- 19
-
W. Chang, S. M. Jang, C. H. Yu, S. C. Sun, and M. S. Liang, ``A manufacturable
and reliable low-k inter-metal dielectric using fluorinated oxide (FSG),''
in Proc. Intl. Interconnect Technology Conference, Burlingame,
California, pp. 131-133, 1999.
- 20
-
A. Loke, J. Wetzel, P. Townsend, T. Tanabe, R. Vrtis, M. Zussman, D. Kumar,
C. Ryu, and S. Wong, ``Kinetics of copper drift in low- polymer
interlevel dielectrics,'' IEEE Trans.Electron Devices, vol. 46, no. 11,
pp. 2178-2187, 1999.
- 21
-
Y. Nishi and R. Doering, Handbook of Semiconductor Manufacturing
Technology.
Marcel Dekker, Inc., 2000.
- 22
-
A. K. Stamper, M. B. Fuselier, and X. Tian, ``Advanced wiring RC delay issues
for sub-0.25-micron generation CMOS,'' in Proc. Intl. Interconnect
Technology Conference, Burlingame, California, pp. 62-64, 1998.
- 23
-
R. Gupta, B. Tutuianu, and L. T. Pileggi, ``The Elmore delay as a bound for
RC trees with generalized input signals,'' IEEE Trans.Computer-Aided
Design of Integrated Circuits and Systems, vol. 16, no. 1, pp. 95-104,
1997.
- 24
-
B. Krauter, S. Mehrotra, and V. Chandramouli, ``Including inductive effects in
interconnect timing analysis,'' in Proc. IEEE Custom Integrated Circuits
Conference, pp. 445-452, 1999.
- 25
-
H. Bakoglu, Circuits, Interconnections and Packaging for VLSI.
Addison-Wesley, 1990.
- 26
-
A. Deutsch, G. V. Kopcsay, P. J. Restle, H. H. Smith, G. Katopis, W. D. Becker,
P. W. Coteus, C. W. Surovic, B. J. Rubin, J. D. R. P., T. Gallo, K. A.
Jenkins, L. M. Terman, R. H. Dennard, G. A. Sai-Halasz, B. L. Krauter, and
D. R. Knebel, ``When are transmission-line effects important for on-chip
interconnections?,'' IEEE Trans.Microwave Theory and Techniques,
vol. 45, no. 10, pp. 1836-1846, 1997.
- 27
-
Y. I. Ismail, E. G. Friedman, and J. L. Neves, ``Figures of merit to
characterize the importance of on-chip inductance,'' in Proc. Design
Automation Conference'98, San Francisco, USA, pp. 560-565, 1998.
- 28
-
M. Bohr, ``Interconnect scaling - the real limiter to high performance
ULSI,'' in in Proc.Intl.Electron Devices Meeting, pp. 241-244, 1995.
- 29
-
J. Davis and J. Meindl, ``Is interconnect the weak link? -- Estimating
wiring requirements of future-generation devices to meet NTRS needs,'' IEEE Circuits & Devices, vol. 14, no. 3, pp. 30-36, 1998.
- 30
-
H. Su and S. Sapatnekar, ``Hybrid structured clock network construction,'' in
Proc. IEEE/ACM International Conference on Computer Aided Design,
San Jose, USA, pp. 333-336, 2001.
- 31
-
S.-C. Wong, G.-Y. Lee, and D.-J. Ma, ``Modeling of interconnect capacitance,
delay, and crosstalk in VLSI,'' IEEE Trans.Semiconductor
Manufacturing, vol. 13, no. 1, pp. 108-111, 2000.
- 32
-
M. Kuhlmann and S. Sapatnekar, ``Exact and efficient crosstalk estimation,''
IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems,
vol. 20, no. 7, pp. 858-866, 2001.
- 33
-
C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, ``A practical
methodology for early buffer and wire resource allocation,'' in Proc.
Design Automation Conference'01, Las Vegas, USA, pp. 189-193, 2001.
- 34
-
M. W. Beattie and L. T. Pileggi, ``IC analyses including extracted inductance
models,'' in Proc. Design Automation Conference'99, New Orleans, USA,
pp. 915-920, 1999.
- 35
-
Y. Massoud, S. Majors, T. Bustami, and J. White, ``Layout techniques for
minimizing on-chip interconnect self inductance,'' in Proc. Design
Automation Conference'98, San Francisco, USA, pp. 566-571, 1998.
- 36
-
K. M. Lepak, I. Luwandi, and L. He, ``Simultaneous shield insertion and net
ordering under explicit RLC noise constraint,'' in Proc. Design
Automation Conference'01, Las Vegas, USA, pp. 199-202, 2001.
- 37
-
J. D. Z. Ma and L. He, ``Formulae and applications of interconnect estimation
considering shield insertion and net ordering,'' in Proc.
IEEE/ACM International Conference on Computer Aided Design, San Jose,
USA, pp. 327-332, 2001.
- 38
-
E. B. Rosa, ``The self and mutual inductances of linear conductors,'' Bulletin of the Bureau of Standards, vol. 4, no. 2, pp. 301-344, 1907.
- 39
-
A. E. Ruehli, ``Inductance calculations in a complex integrated circuit
enviroment,'' IBM J.Res.Dev., vol. 16, no. 1, pp. 470-481, 1972.
- 40
-
F. W. Grover, Inductance Calculations: Working Formulas and Tables.
D. Van Nostrand Company, New York, 1946.
- 41
-
C. Hoer and C. Love, ``Exact inductance equations for rectangular conductors
with applications to more complicated geometries,'' Journal of Research
of the National Bureau of Standards, vol. 69C, no. 2, pp. 127-137, 1965.
- 42
-
Y.-C. Lu, M. Celik, T. Young, and L. T. Pileggi, ``Min/max on-chip inductance
models and delay metrics,'' in Proc. Design Automation Conference'01,
Las Vegas, USA, pp. 341-446, 2001.
- 43
-
M. W. Beattie and L. T. Pileggi, ``Inductance 101: Modeling and extraction,''
in Proc. Design Automation Conference'01, Las Vegas, USA, pp. 323-328,
2001.
- 44
-
D. Sylvester and K. Keutzer, ``A global wiring paradigm for deep submicron
design,'' IEEE Trans.Computer-Aided Design of Integrated Circuits and
Systems, vol. 19, no. 2, pp. 242-252, 2000.
- 45
-
A. Deutsch, P. W. Coteus, G. V. Kopcasy, H. H. Smith, C. W. Surovic,
B. Krauter, D. C. Edelstein, and P. J. Restle, ``On-chip wiring design
challenges for gigahertz operation,'' Proc.IEEE, vol. 89, no. 4,
pp. 529-555, 2001.
- 46
-
A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, R. P.
Dunne, T. A. Gallo, and R. H. Dennard, ``Modeling and characterization of
long on-chip interconnections for high performance microprocessors,'' IBM J.Res.Dev., vol. 39, no. 5, pp. 547-567, 1995.
- 47
-
A. B. Kahng and S. Muddu, ``An analytical delay model for RLC
interconnects,'' IEEE Trans.Computer-Aided Design of Integrated Circuits
and Systems, vol. 16, no. 12, pp. 1507-1514, 1997.
- 48
-
Y. Liang and H. Lei, ``An efficient analytical model of coupled on-chip RLC
interconnects,'' in Proc. Design Automation Conference'01, Las Vegas,
USA, pp. 385-390, 2001.
- 49
-
H. A. Wheeler, ``Formulas for the skin effect,'' Proc.IRE, vol. 2,
no. 10, pp. 412-424, 1942.
- 50
-
A. E. Ruehli and A. C. Cangellaris, ``Progress in the methodologies for the
electrical modeling of interconnections and electronic packages,'' Proc.IEEE, vol. 89, no. 5, pp. 740-771, 2001.
- 51
-
S. Donnay, P. Pieters, K. Vaesen, W. Diels, P. Wambacq, W. de Raedt, E. Beyne,
M. Engels, and I. Bolsens, ``Chip-package codesign of a low-power 5-GHz
RF front end,'' Proc.IEEE, vol. 88, no. 10, pp. 1583-1597, 2000.
- 52
-
J. Post, ``Optimizing the design of spiral inductors on silicon,'' IEEE
Trans.Circuits and Systems-II: Analog and Digital Signal Processing,
vol. 47, no. 1, pp. 15-17, 2000.
- 53
-
J. Burghartz, ``Progress in RF inductors on silicon -- Understanding
substrate losses,'' in Proc.Intl.Electron Devices Meeting,
pp. 523-526, 1998.
- 54
-
C. Yue and S. Wong, ``On-chip spiral inductors with patternd ground shields for
Si-based RF IC's,'' IEEE J.Solid-State Circuits, vol. 33, no. 5,
pp. 743-752, 1998.
- 55
-
A. Zolfaghari, A. Chan, and B. Razavi, ``Stacked inductors and transformers in
CMOS technology,'' IEEE J.Solid-State Circuits, vol. 36, no. 4,
pp. 620-628, 2001.
- 56
-
H.-S. Kim, D. Zheng, A. Becker, and Y.-H. Xie, ``Spiral inductors on Si
p/p substrates with resonant frequency of 20 GHz,'' IEEE Electron
Device Lett., vol. 22, no. 6, pp. 275-277, 2001.
- 57
-
C. H. Chen, Y. K. Fang, C. W. Yang, and C. S. Tang, ``A deep submicron CMOS
process compatible suspending high-Q inductor,'' IEEE Electron Device
Lett., vol. 22, no. 11, pp. 522-523, 2001.
- 58
-
D. C. Edelstein and J. N. Burghartz, ``Spiral and solenoidal inductor
structures on silicon using Cu-damascene interconnects,'' in Proc.
Intl. Interconnect Technology Conference, Burlingame, California,
pp. 18-20, 1998.
- 59
-
C.-C. Tang, C.-H. Wu, and S.-I. Liu, ``Miniature 3-D inductors in standard
CMOS process,'' IEEE J.Solid-State Circuits, vol. 37, no. 4,
pp. 471-480, 2002.
- 60
-
G. Lihui, Y. Mingbin, C. Zhen, H. Han, and Z. Yi, ``High q multilayer spiral
inductor on silicon chip for 5-6 ghz,'' IEEE Electron Device Lett.,
vol. 23, no. 8, pp. 470-472, 2002.
- 61
-
S. Jenei, B. Nauwelaers, and S. Decoutere, ``Physics-based closed-form
inductance expression for compact modeling of integrated spiral inductors,''
IEEE J.Solid-State Circuits, vol. 37, no. 1, pp. 77-80, 2002.
- 62
-
S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, ``Simple
accurate expressions for planar spiral inductances,'' IEEE J.Solid-State
Circuits, vol. 34, no. 10, pp. 1419-1424, 1999.
- 63
-
S. Lee and S. Kim, ``Spiral inductor design for quality factor,'' J.Semiconductor Technology and Science, vol. 2, no. 1, pp. 56-58, 2002.
- 64
-
R. Sabelka, R. Martins, and S. Selberherr, ``Accurate layout-based interconnect
analysis,'' in Proc. Simulation of Semiconductor Processes and Devices
(K. D. Meyer and S. Biesemans, eds.), pp. 336-339, Leuven, Belgium:
Springer, 1998.
- 65
-
W. Pyka, Feature Scale Modeling for Etching and Deposition Processes in
Semiconductor Manufacturing.
Dissertation, Technische Universität Wien, 2000.
http://www.iue.tuwien.ac.at/phd/pyka.
- 66
-
E. Bär, J. Lorenz, and H. Ryssel, ``Three-dimensional simulation of contact
hole metallization using aluminum sputter deposition at elevated
temperatures,'' in Proc. 27th European Solid-State Device Research
Conference (H. Grünbacher, ed.), Stuttgart, Germany, 1997.
- 67
-
P. Fleischmann, W. Pyka, and S. Selberherr, ``Mesh generation for application
in technology CAD,'' IEICE Trans.Electron., vol. E82-C, no. 6,
pp. 937-947, 1999.
- 68
-
J. Ruppert, Results on Triangulation and High Quality Mesh Generation.
PhD thesis, University of California at Berkeley, 1992.
- 69
-
M. Bern and D. Eppstein, ``Mesh generation and optimal triangulation,'' in Computing in Euclidean Geometry (F. K. Hwang and D.-Z. Du, eds.), World
Scientific, 1992.
- 70
-
J. R. Shewchuk, Delaunay Refinement Mesh Generation.
PhD thesis, Computer Science Department, Carnegie Mellon University,
1997.
- 71
-
P. Fleischmann, R. Sabelka, A. Stach, R. Strasser, and S. Selberherr, ``Grid
generation for three-dimensional process and device simulation,'' in Proc. Simulation of Semiconductor Processes and Devices, Tokyo, Japan,
pp. 161-166, 1996.
- 72
-
J. R. Shewchuk, ``Triangle: Engineering a 2D quality mesh generator and
Delaunay triangulator,'' in Proc. First Workshop on Applied
Computational Geometry, pp. 124-133, 1996.
- 73
-
P. Fleischmann and S. Selberherr, ``Three-dimensional Delaunay mesh
generation using a modified advancing front approach,'' in Proc. 6th
Intl. Meshing Roundtable, Park City, Utah, pp. 267-278, 1997.
- 74
-
P. Fleischmann and S. Selberherr, ``A new approach to fully unstructured
three-dimensional Delaunay mesh generation with improved element quality,''
in Proc. Simulation of Semiconductor Processes and Devices, Tokyo,
Japan, pp. 129-130, 1996.
- 75
-
K. Simonyi, Theoretische Elektrotechnik.
Dt. Verl. d. Wiss./Berlin, 1977.
- 76
-
J. Jackson, Klassische Elektrodynamik.
John Wiley & Sons, 1999.
- 77
-
H. Grabinski, Theorie und Simulation von Leitbahnen.
Springer, 1991.
- 78
-
R. Sabelka and S. Selberherr, ``A finite element simulator for
three-dimensional analysis of interconnect structures,'' Microelectronics Journal, vol. 32, no. 2, pp. 163-171, 2001.
- 79
-
A. Ringhandt and H. Wagemann, ``An exact calculation of the two-dimensional
capacitance of a wire and a new approximation formula,'' IEEE
Trans.Electron Devices, vol. 40, no. 5, pp. 1028-1032, 1993.
- 80
-
A. Ruehli and P. Brennan, ``Capacitance models for integrated circuit
metallization wires,'' IEEE J.Solid-State Circuits, vol. SC-10, no. 6,
pp. 530-536, 1975.
- 81
-
P. Wright and Y. Shih, ``Capacitance of top leads metal-comparison between
formula, simulation, and experiment,'' IEEE Trans.Computer-Aided
Design, vol. 12, no. 12, pp. 1897-1902, 1993.
- 82
-
U. Choudhury and A. Sangiovanni-Vincentelli, ``Automatic generation of
analytical models for interconnect capacitances,'' IEEE
Trans.Computer-Aided Design, vol. 14, no. 4, pp. 470-480, 1995.
- 83
-
N. Arora, K. Raol, R. Schumann, and L. Richardson, ``Modeling and extraction of
interconnect capacitances for multilayer VLSI circuits,'' IEEE
Trans.Computer-Aided Design, vol. 15, no. 1, pp. 58-67, 1996.
- 84
-
S.-C. Wong, P. S. Liu, J.-W. Ru, and S.-T. Lin, ``Interconnect capacitance
models for VLSI circuits,'' Solid-State Electronics, vol. 42, no. 6,
pp. 696-977, 1998.
- 85
-
K. Nabors and J. White, ``FastCap: A multipole accelerated 3-D capacitance
extraction program,'' IEEE Trans.Computer-Aided Design, vol. 10,
no. 11, pp. 1447-1459, 1991.
- 86
-
F. Beeftink, A. J. van Genderen, N. P. van der Meijs, and J. Poltz,
``Deep-submicron ULSI parasitics extraction using SPACE,'' in Proc.
Design, Automation and Test in Europe Conference, Designer Track,
pp. 81-86, 1998.
- 87
-
M. W. Beattie and L. T. Pileggi, ``Bounds for BEM capacitance extraction,''
in Proc. Design Automation Conference'97, Anaheim, USA, pp. 133-136,
1997.
- 88
-
M. Bächtold, J. G. Korvink, and H. Baltes, ``Enhanced multipole
acceleration technique for the solution of large Poisson computations,''
IEEE Trans.Computer-Aided Design, vol. 15, no. 12, pp. 1541-1546,
1996.
- 89
-
P. J. H. Elias and G. P. J. F. M. Maas, ``Matrix reduction in IC and PCB
parasitics extraction programs,'' in Proc. ProRISC IEEE Benelux Workshop
on Circuits, Systems and Signal Processing, pp. 143-148, 1996.
- 90
-
Z.-Q. Ning, P. M. Dewilde, and F. L. Neerhoff, ``Capacitance coefficients for
VLSI multilevel metallization lines,'' IEEE Trans.Electron Devices,
vol. ED-34, no. 3, pp. 644-649, 1987.
- 91
-
A. M. Niknejad, R. Gharpurey, and R. G. Meyer, ``Numerically stable Green
function for modeling and analysis of substrate coupling in integrated
circuits,'' IEEE Trans.Computer-Aided Design of Integrated Circuits and
Systems, vol. 17, no. 4, pp. 305-315, 1998.
- 92
-
A. Hieke, ``Simple ADPL implementation of a 3D FEM simulator for mutual
capacitances of arbitrary shaped objects like interconnects,'' in Proc.
2nd Intl. Conf. on Modeling and Simulation of Microsystems, San Juan, Puerto
Rico, USA, pp. 172-175, 1999.
- 93
-
E. B. Nowacka and N. P. van der Meijs, ``The hybrid element method for
capacitance extraction in a VLSI layout verification system,'' in Proc. Software for Electrical Engineering Analysis and Design (P. P.
Silvester, ed.), Pisa, Italy, pp. 125-134, 1996.
- 94
-
A. Zemanian, R. Tewarson, C. Ju, and J. Jen, ``Three-dimensional capacitance
computations for VLSI/ULSI interconnections,'' IEEE
Trans.Computer-Aided Design, vol. 8, no. 12, pp. 1319-1326, 1989.
- 95
-
R. Mittra, W. D. Becker, and P. H. Harms, ``A general purpose Maxwell solver
for the extraction of equivalent circuits of electronic package components
for circuit simulation,'' IEEE Trans.Circuits and
Systems-I: Fundamental Theory and Applications, vol. 39, no. 11,
pp. 964-973, 1992.
- 96
-
L. Yin, J. Wang, and W. Hong, ``A novel algorithm based on the
domain-decomposition method for the full-wave analysis of 3-D
electromagnetic problems,'' IEEE Trans.Microwave Theory and Techniques,
vol. 50, no. 8, pp. 2011-2017, 2002.
- 97
-
G. D. Kondylis, F. D. Flaviis, G. J. Pottie, and T. Itoh, ``A memory-efficient
formulation of the finite-difference time-domain method for the solution of
Maxwell equations,'' IEEE Trans.Microwave Theory and Techniques,
vol. 49, no. 7, pp. 1310-1320, 2001.
- 98
-
C. C.-P. Chen, L. Tae-Woo, N. Murugesan, and S. C. Hagness, ``Generalized
FDTD-ADI: An unconditionally stable full-wave Maxwell's equations solver
for VLSI interconnect modeling,'' in Proc. IEEE/ACM
International Conference on Computer Aided Design, San Jose, USA,
pp. 156-163, 2000.
- 99
-
Y. L. Le Coz and R. B. Iverson, ``A high-speed capacitance extraction algorithm
for multi-level VLSI interconnects,'' in Proc. VLSI Multilevel
Interconnection Conf., Santa Clara, CA, pp. 364-366, 1991.
- 100
-
M. Bächtold, M. Spasojevic, C. Lage, and P. Ljung, ``A system for full-chip
and critical net parasitic extraction for ULSI interconnects using a fast
3-D field solver,'' IEEE Trans.Computer-Aided Design of Integrated
Circuits and Systems, vol. 19, no. 3, pp. 325-338, 2000.
- 101
-
M. Horowitz and R. W. Dutton, ``Resistance extraction from mask layout data,''
IEEE Trans.Computer-Aided Design, vol. CAD-2, no. 3, pp. 145-150,
1983.
- 102
-
A. E. Ruehli, ``Inductance calculations in a complex integrated circuit
environment,'' IBM J.Res.Dev., vol. 16, no. 5, pp. 470-481, 1972.
- 103
-
W. T. Weeks, L. L. Wu, M. F. McAllister, and A. Singh, ``Resistive and
inductive skin effect in rectangular conductors,'' IBM J.Res.Dev.,
vol. 23, no. 6, pp. 652-660, 1979.
- 104
-
A. Ruehli, ``Survey of computer-aided electrical analysis of integrated circuit
interconnections,'' IBM J.Res.Dev., vol. 23, no. 6, pp. 626-639, 1979.
- 105
-
A. E. Ruehli, N. Raver, and P. A. Brennan, ``Three-dimensional inductance
computations with partial element equivalent circuits,'' IBM
J.Res.Dev., vol. 23, no. 6, pp. 661-668, 1979.
- 106
-
M. Kamon, M. J. Tsuk, and J. White, ``FastHenry: A multipole accelerated
3-D inductance extraction program,'' IEEE Trans.Microwave Theory and
Techniques, vol. 42, no. 9, pp. 1750-1758, 1994.
- 107
-
K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao, ``Inductance 101:
Analysis and design issues,'' in Proc. Design Automation Conference'01,
Las Vegas, USA, pp. 329-334, 2001.
- 108
-
H. Heeb and A. E. Ruehli, ``Three-dimensional interconnect analysis using
partial element equivalent circuits,'' IEEE Trans.Circuits and
Systems-I: Fundamental Theory and Applications, vol. 39, no. 11,
pp. 974-982, 1992.
- 109
-
Y. Cao, Z.-F. Li, J.-F. Mao, and J.-F. Mao, ``A PEEC with a new capacitance
model for circuit simulation of interconnects and packaging structure,'' IEEE Trans.Microwave Theory and Techniques, vol. 48, no. 2, pp. 281-287,
2000.
- 110
-
J. Cullum, A. E. Ruehli, and T. Zhang, ``A method for reduced-order modeling
and simulation of large interconnect circuits and its application to PEEC
models with retardation,'' IEEE Trans.Circuits and Systems-II: Analog
and Digital Signal Processing, vol. 47, no. 4, pp. 261-273, 2000.
- 111
-
M. Kamon, N. Marques, and J. White, ``FastPep: A fast parasitic extraction
program for complex three-dimensional geometries,'' in Proc. Intl.Conf.
Computer Aided Design, San Jose, California, pp. 456-460, 1997.
- 112
-
A. M. Niknejad and R. G. Meyer, ``Analysis and optimization of monolithic
inductors and transformers for RF ICs,'' in Proc. IEEE Custom
Integrated Circuits Conference, pp. 375-378, 1997.
- 113
-
G. Leonhardt and W. Fichtner, ``Acceleration of inductance extraction by means
of the Monte Carlo method,'' in Proc. 2nd Intl. Conf. on Modeling
and Simulation of Microsystems, San Juan, Puerto Rico, USA, pp. 147-150,
1999.
- 114
-
P. Böhm and G. Wachutka, ``Transient electromagnetic behavior of multiply
contacted interconnect,'' in Proc. 2nd Intl. Conf. on Modeling and
Simulation of Microsystems, San Juan, Puerto Rico, USA, pp. 301-304, 1999.
- 115
-
O. Bíró and K. Preis, ``On the use of the magnetic vector potential in
the finite-element analysis of three-dimensional eddy currents,'' IEEE
Trans.Magnetics, vol. 25, no. 4, pp. 3145-3159, 1989.
- 116
-
C. Schuster, A. Witzig, and W. Fichtner, ``Electromagnetic analysis of
interconnects using the finite difference time domain method,'' Tech. Rep.
99/17, Integrated Systems Laboratory, ETH Zürich, 1999.
- 117
-
W. Schoenmaker and P. Meuris, ``Electromagnetic interconnects and passives
modeling: Software implementation issues,'' IEEE Trans.Computer-Aided
Design of Integrated Circuits and Systems, vol. 21, no. 5, pp. 534-543,
2002.
- 118
-
W. Schoenmaker, W. Magnus, and P. Meuris, ``Ghost fields in classical gauge
theories,'' Physical Review Letters, vol. 88, no. 18,
pp. 181602-1--181602-4, 2002.
- 119
-
P. Meuris, W. Schoenmaker, and W. Magnus, ``Strategy for electromagnetic
interconnect modeling,'' IEEE Trans.Computer-Aided Design of Integrated
Circuits and Systems, vol. 20, no. 6, pp. 753-762, 2001.
- 120
-
A. Devgan, H. Ji, and W. Dai, ``Analysis and design of transmission-line
structures by means of the geometric mean distance,'' in Proc. IEEE
AFRICON 4th, vol. 2, pp. 1062-1065, 1996.
- 121
-
M. W. Beattie, B. Krauter, L. Alatan, and L. T. Pileggi, ``Equipotential shells
for efficient inductance extraction,'' IEEE Trans.Computer-Aided Design
of Integrated Circuits and Systems, vol. 20, no. 1, pp. 317-320, 2001.
- 122
-
A. Devgan, H. Ji, and W. Dai, ``How to efficiently capture on-chip inductance
effects: Introducing a new circuit element k,'' in Proc. IEEE/ACM
International Conference on Computer Aided Design, San Jose, USA,
pp. 150-155, 2000.
- 123
-
H. Ji, A. Devgan, and W. Dai, ``KSim: A stable and efficient RKC simulator
for capturing on-chip inductance effect,'' in Proc. Design Automation
Conference'01, Las Vegas, USA, pp. 379-384, 2001.
- 124
-
P. J. H. Elias, ``Efficient moments extraction from VLSI interconnections,''
in Proc. ProRISC/IEEE Benelux Workshop on Circuits, Systems and Signal
Processing, Mierlo, The Netherlands, pp. 83-90, 1995.
- 125
-
P. J. H. Elias and N. P. van der Meijs, ``Efficient moments extraction of large
inductively coupled interconnection networks,'' in Proc. Intl. Symposium
on Circuits and Systems, vol. 4, Atlanta, Georgia, pp. 540-543, 1996.
- 126
-
A. Odabasioglu, M. Celik, and L. T. Pileggi, ``PRIMA: Passive reduced-order
interconnect macromodeling algorithm,'' IEEE Trans.Computer-Aided Design
of Integrated Circuits and Systems, vol. 17, no. 8, pp. 645-654, 1998.
- 127
-
K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu, ``On thermal
effects in deep sub-micron VLSI interconnects,'' in Proc. Design
Automation Conference'99, New Orleans, USA, pp. 885-891, 1999.
- 128
-
X. Gui, S. Dew, and M. Brett, ``Thermal simulation of thin-film interconnect
failure caused by high current pulses,'' IEEE Trans.Electron Devices,
vol. 42, no. 7, pp. 1386-1388, 1995.
- 129
-
P. Waltz, G. Lormand, and L. Arnaud, ``Thermal analytical model for analysis of
pulsed DC electromigration results,'' in Proc. 27th European
Solid-State Device Research Conference (H. Grünbacher, ed.), Stuttgart,
Germany, 1997.
- 130
-
W. Schoenmaker and V. Petrescu, ``The modeling of electromigration: A new
challenge for TCAD?,'' in Proc. Simulation of Semiconductor Processes
and Devices (K. D. Meyer and S. Biesemans, eds.), Leuven, Belgium,
pp. 328-331, 1998.
- 131
-
S. H. Kang and E. Shin, ``A three-dimensional nonlinear analysis of
electromigration-induced resistance change and Joule heating in
microelectronic interconnects,'' Solid-State Electron., vol. 45, no. 2,
pp. 341-346, 2001.
- 132
-
A. S. Oates, ``Electromigration failure of contacts and vias in sub-micron
integrated circuit metallizations,'' Microelectron.Reliab., vol. 36,
no. 7/8, pp. 925-953, 1996.
- 133
-
O. Zienkiewicz and R. Taylor, Basic Formulation and Linear Problems,
vol. 1 of The Finite Element Method.
London: McGraw-Hill, fourth ed., 1989.
- 134
-
K.-J. Bathe, Finite-Elemente-Methoden.
Springer, 1990.
- 135
-
J. R. Shewchuk, ``An introduction to the conjugate gradient method without the
agonizing pain.'' http://www-2.cs.cmu.edu/~jrs/jrspapers.html, 1994.
- 136
-
H. Schwarz, Numerische Mathematik.
Stuttgart: Teubner, 1997.
4. Auflage.
- 137
-
A. H. Stroud, Approximate Calculation of Multiple Integrals.
Prentice-Hall, Englewood Cliffs, N.J., 1971.
- 138
-
A. H. Stroud, ``Some approximate integration formulas of degree 3 for an
n-dimensional simplex,'' Numer.Math., vol. 9, no. 1, pp. 38-45, 1966.
- 139
-
A. H. Stroud, ``Approximate integration formulas of degree 3 for simplexes,''
Math.Comp., vol. 18, no. 4, pp. 590-597, 1964.
- 140
-
A. Krommer and C. Überhuber, Computational Integration.
SIAM, 1998.
- 141
-
R. Rubinstein, Simulation and the Monte Carlo Method.
John Wiley and Sons, 1981.
- 142
-
S. Mohan, C. Yue, M. del Mar Hershenson, S. Wong, and T. Lee, ``Modeling and
characterisation of on-chip transformers,'' in Proc.Intl.Electron
Devices Meeting, pp. 531-534, 1998.
- 143
-
J. Long, ``Monolithic transformers for silicon RF IC design,'' IEEE
J.Solid-State Circuits, vol. 35, no. 9, pp. 1368-1382, 2000.
- 144
-
C. Harlander, R. Sabelka, and S. Selberherr, ``Inductance calculation in
interconnect structures,'' in Proc. 3rd Intl. Conf. on Modeling and
Simulation of Microsystems, San Diego, California, USA, pp. 416-419, 2000.
- 145
-
A. Kost, Numerische Methoden in der Berechnung elektromagnetischer
Felder.
Springer-Verlag, Berlin Heidelberg, 1994.
- 146
-
O. Bíró and K. R. Richter, ``CAD in electromagnetism,'' Advances
in Electronics and Electron Physics, vol. 82, no. 1, pp. 1-96, 1991.
- 147
-
H. Stögner, Anwendung der Methode der Finiten Elemente zur numerischen
Berechnung dreidimensionaler elektromagnetischer Felder.
Habilitation, Technische Universität Graz, 1987.
C. Harlander: Numerische Berechnung von Induktivitäten in dreidimensionalen Verdrahtungsstrukturen