2.2.9 Micromechanics in TCAD

The materials involved in typical microelectronic systems are subject to very strong mechanical constrictions due to the rigorous embedding in hard and rigid material compounds. Thus, the microscopic behavior can be assumed to be in steady state in which the mechanical movements can be neglected. Of course, there are still diffusion processes involved, but their time scale, e.g. their diffusion constant, is much smaller than the investigated time regime to determine the mechanical burden. Hence, the thermo-mechanical and electro-thermal investigations can be independently executed very efficiently using tuned simulators for each of the sub-problems. After a certain time, at which the mechanical burden has reached a critical value, the thermo-mechanical sub-system has to be updated to follow a self-consistent iteration scheme for the globally coupled electric, thermal, mechanical problem.

Microelectronical and micromechanical (MEMS) devices often use micro-scaled phenomena of coupled electro-thermal and thermo-mechanical subsystems including also mass flows. Therefore, the assumption of velocity-free material regions remains no longer valid for these systems and a rigorous treatment of the mechanical and electrical phenomena has to be performed.

However, TCAD applications require micromechanical considerations beside rigorous thermo-electrical analysis as recent survey and forecast have shown to overcome scaling-induced problems, e.g. enhanced thermal stress cycles, electro-migration, and current densities [3]. Hence high mechanical demands have appeared not only for devices but also for interconnect structures and chip packages. According to recently announced requirements by the ITRS [3], thermal issues have reached certain critical levels which make an additional micromechanical analysis necessary to fulfill the challenging ITRS goals proposed for the future.

The mechanical strain on various materials shows different effects. Device engineers have successfully developed some applications where the strain can be advantageously used. This strain engineering has been implemented in state-of-the-art technology nodes in semiconductor device fabrication for instance to align the carrier charge mobilities in nMOS and pMOS transistors. In addition, the enhancement factor an be adapted to a certain desired level that the mobility for both, the electrons in the nMOS transistors and the holes in the pMOS transistors have the same values which idealizes CMOS circuits loss during transistors switching [101]. This technique used the advantageous crystal structure of semiconductor materials, for instance ${\mathrm{Si}}$ and ${{\mathrm{SiGe}}}$ . In this particular example, strained materials are introduced to CMOS structures. Since the charge carriers in these transistors have different mobility tensors, the resistivity as well as the transition times of the transistors can be adjusted to customize the overall performance of the circuit [102,103]. The main application of strain engineering in the semiconductor device regime deals with mobility enhancements and the equalizing of carrier mobilities of nMOS and pMOS transistors in CMOS circuits due to compressive and tensile stress profiles [102,103].

However, strain engineering is not limited to mobility enhancements in CMOS circuits. Many different materials are currently under development for various applications, e.g. ${{\mathrm{SiGe}}}$ [103], ${\mathrm{SiC}}$ [104], ${\mathrm{GaN}}$ [105,106,107,108]. A promising application for strain engineering is the control of optical and electro-magnetical properties as well as the exploitation of their anisotropy for future device applications [106].

However, modern microelectronic devices are very sensitive to variations of stress levels in certain device layers, e.g. in the channel of a transistor or at edges of thin film dielectrics. The stress changes the lattice configuration slightly and therefore also the bandgap and the mobility inside the channel. Also, the breakdown voltage of the dielectric material can be dramatically influenced [109]. As already mentioned, one consequence of mechanical strain is the lattice deformation which can be exploited to enhance the charge carrier mobility or to slightly change the bandgap in semiconductor and dielectric materials [109]. Unfortunately, these two effects appear unexpectedly during fabrication processes or under critical operation conditions where the device characteristics and/or the device performance is permanently changed. For instance, if a rather thick ${{\mathrm{SiGe}}}$ layer over a ${\mathrm{Si}}$ substrate is deposited, the intrinsic lattice constant of ${\mathrm{Si}}$ is forced to a few tens ${{\mathrm{SiGe}}}$ atomic layers, where the enforcement to the ${{\mathrm{SiGe}}}$ lattice distance reduces with increasing distance form the ${\mathrm{Si}}$ - ${{\mathrm{SiGe}}}$ interface. If in this case additional stress occurs in combination with high temperatures due to high work load. The intrinsic stress due to the lattice mismatch between the ${{\mathrm{SiGe}}}$ and ${\mathrm{Si}}$ can be loose mechanical contact due to adhesion loss at the interface or due to cracks in the ${{\mathrm{SiGe}}}$ layer. Another unfavorable effect due to mechanical strain are drifting ions since the deformed crystal lattice provides lower activation energies for ion diffusion and moving ions out of their lattice site. Hence, the temperature as well as the mechanical strain have to be considered carefully to obtain device structures which can act also under high loads and at high temperatures within reliability requirements.

Stefan Holzer 2007-11-19