Bibliography

1

P.J. Mohr and B.N. Taylor,
``CODATA Recommended Values of the Fundamental Physical Constants: 2002'',
Rev.Mod.Phys., vol. 77, no. 1, pp. 1-107, 2005.

2

Intel Corporation,
``Microprocessor Hall of Fame'', 2004,
http://www.intel.com.

3

Semiconductor Industry Association,
``International Technology Roadmap for Semiconductors - 2005 Edition'', 2005,
http://public.itrs.net.

4

K. Banarjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C.M. Hu,
``On Thermal Effects in Deep Sub-Micron VLSI Interconnects'',
in Proc. 1999 IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 1999, pp. 885-891.

5

K. Banarjee and A. Mehrotra,
``Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets'',
Proc. 2001 International Conference on Computer-Aided Design, pp. 158-164, 2001.

6

G.E. Moore,
``Cramming More Components Onto Integrated Circuits'',
Electronics, pp. 114-117, Apr. 1965.

7

R.R. Schaller,
``Moore's Law: Past, Present, and Future'',
IEEE Spectrum, vol. 34, no. 6, pp. 53-59, June 1997.

8

G.E. Moore,
``Progress in Digital Integrated Electronics'',
Proc.IEDM Tech.Dig, vol. 19, pp. 11-13, 1975.

9

G.E. Moore,
``Lithography and the Future of Moore's Law'',
in Optical/Laser Microlithography VIII, T.A. Brunner, Ed. 1995, vol. 2440, pp. 2-17, SPIE.

10

Semiconductor Industry Association,
``International Technology Roadmap for Semiconductors - 2003 Edition'', 2003,
http://public.itrs.net.

11

Semiconductor Industry Association,
``International Technology Roadmap for Semiconductors - 2004 Update'', 2004,
http://public.itrs.net.

12

K. Banerjee and A. Mehrotra,
``Global (Interconnect) Warming'',
IEEE Spectrum, pp. 16-32, Sept. 2001.

13

J.S. Kilby,
``Miniaturized Self-Contained Cicuit Module and Method of Fabrication'', U.S. Patent US03138744,
filed May 6, 1959; issued June 23, 1964.

14

J.S. Kilby,
``Semiconductor Device'', U.S. Patent US03643138,
Filed January 29, 1962; issued February 15, 1972.

15

L. Smith, V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, M. Jurczak, D. Pramanik, and K. De Meyer,
``Exploring the Limits of Stress-Enhanced Hole Mobility'',
IEEE Electron Device Lett., vol. 26, no. 9, pp. 652-654, 2005.

16

F. Nouri, P. Verheyen, L. Washington, V. Moroz, I. De Wolf, M. Kawaguchi, S. Biesemans, R. Schreutelkamp, Y. Kim, M. Shen, X. Xu, R. Rooyackers, M. Jurcak, G. Eneman, K. De Meyer, L. Smith, D. Pramanik, H. Forstner, S. Thirupapuliyur, and G.S. Higashi,
``A Systematic Study of Trade-offs in Engineering a Locally Strained pMOSFET'',
in Proc.IEDM Tech.Dig [107], pp. 1055-1058,
0-7803-8684-1.

17

A. Gehring and S. Selberherr,
``Gate Current Modeling for MOSFETs'',
Journal of Computational and Theoretical Nanoscience, vol. 2, no. 1, pp. 26-44, 2005.

18

A. Gehring,
Simulation of Tunneling in Semiconductor Devices,
Dissertation, Technische Universität Wien, 2003,
http://www.iue.tuwien.ac.at/phd/gehring.

19

T.D. Sullivan,
``Reliability Considerations for Copper Metallizations in ULSI Circuits'',
in Conf.Proc. American Institute of Physics, 1999, vol. 491, pp. 39-50.

20

A. Isobayashi, Y. Enomoto, H. Yamada, S. Takahashi, and S. Kadomura,
``Thermally Robust Cu Interconnects with Cu-Ag Alloy for sub 45nm Node'',
in Proc.IEDM Tech.Dig [107], pp. 953-956,
0-7803-8684-1.

21

D. Ryuzaki, H. Sakurai, K. Abe, K. Takeda, and H. Fukada,
``Enhanced Dielectric-Constant Reliability of Low-$\kappa$ Porous Organosilicate Glass ( $\kappa=2.3$ ) for 45-nm-Generation Cu Interconnects'',
in Proc.IEDM Tech.Dig [107], pp. 949-952,
0-7803-8684-1.

22

D.S. Yu, A. Chin, C.C. Laio, C.F. Lee, C.F. Cheng, W.J. Chen, C. Zhu, M.-F. Li, W.J. Yoo, S.P. McAlister, and D.L. Kwong,
``3D GOI CMOSFETs with novel IrO$_2$ (Hf) Dual Gates and high-$\kappa$ Dielectric on 1P6M-18$\mu$ m-CMOS'',
in Proc.IEDM Tech.Dig [107], pp. 181-184,
0-7803-8684-1.

23

M. Miyoshi, A. Imanishi, H. Ishikawal, T. Egawal, K. Asai, M. Mouri, T. Shibata, M. Tanaka, and O. Oda,
``Growth and Characterization of AlGaN/AlN/GaN HEMTs on 100-mm-diameter Epitaxial AlN/Sapphire Templates'',
in Proc.IEDM Tech.Dig [107], pp. 1031-1034,
0-7803-8684-1.

24

V. Gutmann and E. Hengge,
Anorganische Chemie,
VCH Verlagsgesellschaft mbH, 1990.

25

W. Harth,
Halbleitertechnologie,
Teubner, 1981.

26

J.S. Reid, X. Sun, E. Kolawa, and M.-A. Nicolet,
``Ti-Si-N Diffusion Barriers Between Silicon and Copper'',
IEEE Electron Device Lett., vol. 15, no. 8, pp. 298-300, 1994.

27

S.S. Ang and W.D. Brown,
``Tantalum Oxide Dielectric for Embedded Capacitor Applications'',
in Proc. 6th Intl. Conf. on Properties and Application of Dielectric Materials, June 2000, pp. 841-844.

28

J.A. Mandarino and M.E. Back,
Fleischer's Glossary of Mineral Species 2004,
Mineralogical Record, ninth edition edition, 2004.

29

K. Hieda, K. Eguchi, N. Fukushima, T. Aoyama, K. Natori, M. Kiyotoshi, S. Yamazaki, M. Izuha, S. Niwa, Y. Fukuzumi, Y. Ishibashi, Y. Kohyama, T. Arikado, and K. Okumura,
``All Perovskite Capacitor (APEC) Technology for (Ba,Sr)TiO$_3$ Capacitor Scaling Toward $0.10 \mu$ m Stacked DRAMs'',
in Proc.IEDM Tech.Dig, San Francisco, CA, Dec. 1998, pp. 807-810,
0-.

30

U. Tietze and C. Schenk,
Halbleiterschaltungstechnik,
Springer-Verlag, 10 edition, 1993.

31

S.M. Sze, Ed.,
VLSI Technology,
McGraw-Hill, New York, second edition, 1988.

32

G. Schindler,
``Reliability of Narrow Copper Interconnects'',
in Semicon 2005, Munich, Germany, Mar. 2005.

33

O. Aubel,
Ultrahochbeschleunigte Lebensdauertests an modernen Kupfer-Leiterbahnsystemen in höchstintegrierten Schaltungen,
Dissertation, Universität Hannover, 2004.

34

J.Y. Park, Y.H. Lee, J.W. Bae, G.Y. Yeom, and J.H. Song,
``MoSi(N) As A Diffusion Barrier Between Cu And Si'',
in Intl. Microprocesses and Nanotechnology Conference, July 1998, pp. 248-250.

35

S.C. Sun, H.K. Yap, C.A. Chen, and P. Lin,
``Evaluation of Amorphous (Ta,W,Mo)-Si-N Diffusion Barriers Between Cu and Si'',
in Proc. 6th Intl. Conf. on Solid-State and Integrated-Circuit Technology, Oct. 2001, vol. 1, pp. 397-399.

36

H. Ceric,
Numerical Techniques in Interconnect and Process Simulation,
Dissertation, Technische Universität Wien, 2005,
http://www.iue.tuwien.ac.at/phd/ceric.

37

Institut for Microelectronics,
MINIMOS-NT 2.1 User's Guide,
Technische Universität Wien, Austria, 2004,
http://www.iue.tuwien.ac.at/software.

38

ISE Integrated Systems Engineering AG, Zürich, Switzerland,
DESSIS-ISE, ISE TCAD Release 9.0, Aug. 2003.

39

Institute for Microelectronics,
The Smart Analysis Programs,
Technische Universität Wien, Austria, 2003,
http://www.iue.tuwien.ac.at/software.

40

Synopsys,
TCAD Sentaurus Y-2006.06 User Manual,
Synopsys, Mountain View, 2006.

41

Synopsys,
Taurus Work Bench User Manual,
Synopsys, Mountain View, 2003.

42

ISE Integrated Systems Engineering AG, Zürich, Switzerland,
GENESISe, ISE TCAD Release 10.0, 2004.

43

ISE Integrated Systems Engineering AG, Zürich, Switzerland,
OptimISE, ISE TCAD Release 10.0, 2004.

44

Institute for Microelectronics,
SIESTA - The Simulation Environment for Semiconductor Technology Analysis,
Technische Universität Wien, Austria, 2003,

http://www.iue.tuwien.ac.at/software.

45

N. Konofaos, T. Voilas, and G.P. Alexiou,
``Design and Simulation of an Embedded DRAM Cell Made Up With MOSFETs Having Alternative Gate Dielectrics'',
in SPIE 2005 [350], pp. 598-604.

46

J. Ida, M. Yoshimaru, T. Usami, A. Ohtomo, K. Shimokawa, A. Kita, and M. Ino,
``Reduction of Wiring Capacitance With New Low Dielectric SiOF Interlayer Film for High Speed/Low Power Sub-Half Micron CMOS'',
in 1994 Symponsium on VLSI, Tech.Dig., 1994, pp. 59-60.

47

S. Holzer, R. Minixhofer, C. Heitzinger, J. Fellner, T. Grasser, and S. Selberherr,
``Extraction of Material Parameters Based on Inverse Modeling of Three-Dimensional Interconnect Fusing Structures'',
Microelectronics Journal, vol. 35, no. 10, pp. 805-810, 2004.

48

R. Plasun,
Optimization of VLSI Semiconductor Devices,
Dissertation, Technische Universität Wien, 1999,
http://www.iue.tuwien.ac.at/phd/plasun.

49

R. Plasun, M. Stockinger, R. Strasser, and S. Selberherr,
``Simulation Based Optimization Environment and Its Application to Semiconductor Devices'',
in Intl. Conf. on Applied Modelling and Simulation, Honolulu, HI, Aug. 1998, pp. 313-316.

50

R. Strasser, R. Plasun, M. Stockinger, and S. Selberherr,
``Inverse Modeling of Semiconductor Devices'',
in Proc. SIAM Conference on Optimization 1999, Atlanta, GA, 1999, p. 77.

51

Ch. Pichler, R. Plasun, R. Strasser, and S. Selberherr,
``High-Level TCAD Task Representation and Automation'',
IEEE J.Technology Computer Aided Design, May 1997,

http://www.ieee.org/journal/tcad/accepted/pichler-may97/.

52

H. Pimingstorfer, S. Halama, and S. Selberherr,
``A TCAD Environment for Process and Device Engineering'',
in Proc. Int. Conf. on VLSI and CAD, Seoul, Korea, Oct. 1991, pp. 280-283.

53

M. Stockinger and S. Selberherr,
``Automatic Device Design Optimization with TCAD Frameworks'',
in Proc. 3rd Intl. Conf. on Modeling and Simulation of Microsystems, San Diego, California, USA, Mar. 2000, pp. 1-6.

54

H. Sato, K. Tsuneno, K. Aoyama, T. Nakamura, H. Kunitomo, and H. Masuda,
``A New Hierarchical RSM for TCAD-based Device Design to Predict CMOS Development'',
in Proc. IEEE 1995 Int. Conf. on Microelectronic Test Structures, Mar. 1995, vol. 8, pp. 299-302.

55

V. Muntés Mulero, J. Aguilar Saborit, J.L. Larriba Pey, and C. Zuzarte,
``A Study of Execution Plan Aware Mutations for Genetic Cyclic Query Optimization'',
Tech. Rep., Universitat Politècnica de Catalunya (UPC), June 2003,
UPC-DAC-2003-37.

56

Technovest(Pty) Ltd.,
The Grail Genetic Optimizer for TradeStation $^{\mathrm{TM}}$ (GGO),

http://www.thegrailsystem.com.

57

J.W. von Goethe,
Faust. Zweiter Theil, in Goethes sämtliche Werke,
Bd. 3,
Verlag der J. G. Cotta'schen Buchhandlung, 1875.

58

H. Hofmann,
Das elektromagnetische Feld,
Springer, Wien, Austia, 3rd edition, 1986.

59

A. Prechtl,
Vorlesungen über Theoretische Elektrotechnik,
Institut für Grundlagen und Theorie der Elektrotechnik, Technische Universität Wien, 1998.

60

H.J. Dirschmid,
Einführung in die mathematischen Methoden der theoretischen Physik,
Vieweg, 1976.

61

K.G. Denbigh,
The Thermodynamics of the Steady State,
Methuen & Co. LTD. London, 1950.

62

S. Selberherr,
Analysis and Simulation of Semiconductor Devices,
Springer, Wien, New York, 1984.

63

R. Stratton,
``Diffusion of Hot and Cold Electrons in Semiconductor Barriers'',
Physical Review B, vol. 126, no. 6, pp. 2002-2014, 1962.

64

D. Chen, E. Li, E. Rosenbaum, and S.M. Kang,
``Interconnect Thermal Modeling for Accurate Simulation of Circuit Timing and Reliability'',
IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems, vol. 19, pp. 197-205, 2000.

65

G.K. Wachutka,
``Rigorous Thermodynamic Treatment of Heat Generation and Conduction in Semiconductor Device Modeling'',
IEEE Trans.Computer-Aided Design, vol. 9, no. 11, pp. 1141-1149, Nov. 1990.

66

K. Kells,
General Electrothermal Semiconductor Device Simulation,
Hartung-Gorre Verlag, Konstanz, 1994.

67

N.W. Ashcroft and N.D. Mermin,
Solid State Physics,
W.B. Saunders, 1976.

68

L. Boltzmann,
Lectures on Gas Theory,
Dover Publications, 1964.

69

Ch. Kittel and H. Kroemer,
Physik der Wärme,
Oldenbourg, 1993.

70

I. Priogine,
The End of Certainty: Time, Chaos and the New Laws of Nature,
The Free Press, 1997.

71

H.S. Leff and A. Rex, Eds.,
Maxwell's Demon: Entropy, Information, Computing,

Princeton University Press, 1990.

72

P.A. Tipler,
Physik,
Spektrum Akademischer Verlag, 2004.

73

D. Kondepudi and I. Prigogine,
Modern Thermodynamics - From Heat Engines to Dissipative Structures,
John Wiley & Sons, New York, 1998.

74

R. Mayer,
``Remarks on the Forces of Nature'',
in Bioenergetics - the Molecular Basis of Biological Energy Transformations. 1971, Benjamin Cummings.

75

M. Planck,
Treatise on Thermodynamics,
Dover Publications, 1897.

76

K.G. Denbigh,
The Principles of Chemical Equilibrium,
Methuen & Co. LTD. London, reprinted edition, 1957.

77

Y. Zhang, J. Christofferson, A. Shakouri, D. Li, A. Majumdar, Y. Wu, R. Fan, and P. Yang,
``Characterization of Heat Transfer Along Silicon Nanowire Using Thermoreflectance Technique'',
IEEE Trans. Nanotechnology, vol. 5, no. 1, pp. 67-74, 2006.

78

D. Li, Y. Wu, P. Kim, L. Shi, P. Yang, and A. Majumdar,
``Thermal Conductivity of Individual Silicon Nanowires'',
J.Appl.Phys., vol. 83, pp. 2934-2936, 2003.

79

A. Nathan and H. Baltes,
Microtransducer CAD,
Springer Verlag, Wien, New York, 1999.

80

G.A. Slack,
``Thermal Conductivity of Pure and Impure Silicon, Silicon Carbide, and Diamond'',
J.Appl.Phys., vol. 35, no. 12, pp. 3460-3466, 1964.

81

S.P. Gaur and D.H. Navon,
``Two-Dimensional Carrier Flow in a Transistor Structure under Nonisothermal conditions'',
IEEE Trans.Electron Devices, vol. 23, no. 1, pp. 50-57, 1976.

82

D.K. Sharma and K.V. Ramanathan,
``Modeling Thermal Effects On MOS I-V Characteristics'',
IEEE Electron Device Lett., vol. 4, no. 10, pp. 362-364, 1983.

83

L. Onsager,
``Reciprocal Relations in Irreversible Processes. I.'',
Physical Review, vol. 37, no. 2, pp. 405-426, 1931.

84

L. Onsager,
``Reciprocal Relations in Irreversible Processes. II.'',
Physical Review, vol. 38, no. 12, pp. 2265-2279, 1931.

85

E. Mendoza,
Reflexions of the Motive Power of Fire by Sadi Carnot and other Papers on the Second Law of Thermodynamics by É. Clapeyron and R. Clausius,
Dover Publications, Inc., Mineola, New York, 2005.

86

L. Boltzmann,
``Zur Theorie der thermoelektrischen Erscheinungen'',
Wiener Berichte, vol. 96, pp. 1258-1297, 1887.

87

M. Knaipp,
Modellierung von Temperatureinflüssen in Halbleiterbauelementen,
Dissertation, Technische Universität Wien, 1998,
http://www.iue.tuwien.ac.at/phd/knaipp.

88

W.R. Tonti, J.A. Fifield, J. Higgins, W.H. Guthrie, W. Berry, and C. Narayan,
``Reliability and Design Qualification of A Sub-Micron Tungsten Silicide E-Fuse'',
in Proc. 42nd Annual Intl. Reliability Physics Symposium, Apr. 2004, pp. 152-156.

89

J. Fellner, P. Boesmueller, and H. Reiter,
``Lifetime Study for a Poly Fuse in a $0.35\mu$ m Polycide CMOS Process'',
in Proc. 43rd Annual Intl. Reliability Physics Symposium, Apr. 2005, pp. 446-449.

90

R. Minixhofer, S. Holzer, C. Heitzinger, J. Fellner, T. Grasser, and S. Selberherr,
``Optimization of Electrothermal Material Parameters Using Inverse Modeling'',
in Proc. 33rd European Solid-State Device Research Conference (ESSDERC 2003), José Franca and Paulo Freitas, Eds., Estoril, Portugal, Sept. 2003, pp. 363-366, IEEE.

91

Y. Taur and T.H. Ning,
Fundamentals of Modern VLSI Devices,
Cambridge University Press, 1998.

92

R. Sabelka and S. Selberherr,
``A Finite Element Simulator for Three-Dimensional Analysis of Interconnect Structures'',
Microelectronics Journal, vol. 32, pp. 163-171, 2001.

93

R. Sabelka and S. Selberherr,
``SAP -- A Program Package for Three-Dimensional Interconnect Simulation'',
in IITC'98 [351], pp. 250-252.

94

A. Nentchev, R. Sabelka, W. Wessner, and S. Selberherr,
``On Chip Interconnect Simulation of Parasitic Capacitances in Periodic Structures'',
in The 2005 European Simulation and Modelling Conference Proceedings, Oct. 2005, pp. 420 - 424.

95

B. Wunderle, R. Schacht, O. Wittler, B. Michel, and E. Reichl,
``Thermal Performance, Mechanical Reliability and Technological Features of Different Cooling Concepts for High Power Chip Modules'',
in 9th Intl. Workshop an THERMal INvestigations of ICs and Systems [352], pp. 59-64,
0-7803-7999-3.

96

F. Ziegler,
Mechanics of Solids and Fluids,
Springer, New York, 1995.

97

O.C. Zienkiewicz,
The Finite Element Method: Basic Formulation and Linear Problems,
McGraw-Hill, England, 1987.

98

T. Belytschko, W.K. Liu, and B. Moran,
Finite Elements for Nonlinear Continua and Structures,
Wiley, 1996.

99

H. Ceric, A. Hoessinger, T. Binder, and S. Selberherr,
``Modeling of Segregation on Material Interfaces by Means of the Finite Element Method'',
in Proc. MATHMOD, Wien, Austria, Feb. 2003, pp. 445-452.

100

C. Hollauer, S. Holzer, H. Ceric, S. Wagner, T. Grasser, and S. Selberherr,
``Investigation of Thermo-Mechanical Stress in Modern Interconnect Layouts'',
in Sixth International Congress on Thermal Stresses, Wien, Austria, May 2005, pp. 637-640.

101

H.S .Yang, R. Malik, S. Narasimha, Y. Li, R. Divakuruni, P. Agnello, S. Allen, A. Antreasyan, J.C. Arnold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarrao, A. Chou, W. Clark, S.W. Crowder, B. Engel, H. Harifuchi, S.F. Huang, R. Jagannathan, F.F. Jamin, Y. Kohyama, H. Kuroda, C.W. Lai, H.K. Lee, W-H. Lee, E.H. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H.Y. Ng, S. Panda, R. Rengarajan, M. Steigerwalt, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S.-P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I.Y. Yang, C.H. Wann, and L.T. Su,
``Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing'',
in Proc.IEDM Tech.Dig [107], pp. 1075-1078,
0-7803-8684-1.

102

S. Dhar, H. Kosina, V. Palankovski, E. Ungersböck, and S. Selberherr,
``Electron Mobility Model for Strained-Si Devices'',
IEEE Trans.Electron Devices, vol. 52, no. 4, pp. 527-533, 2005.

103

S. Smirnov,
Physical Modeling of Electron Transport in Strained Silicon and Silicon-Germanium,
Dissertation, Technische Universität Wien, 2003,
http://www.iue.tuwien.ac.at/phd/smirnov.

104

T. Ayalew,
SiC Semiconductor Devices Technology, Modeling, and Simulation,
Dissertation, Technische Universität Wien, 2004,
http://www.iue.tuwien.ac.at/phd/ayalew.

105

B. Witzigmann, V. Laino, M. Luisier, U. T. Schwarz, H. Fischer, G. Feicht, W. Wegscheider, C. Rumbolz, A. Lell, and V. Härle,
``Analysis of temperature-dependent optical gain in GaN-InGaN quantum-well structures'',
IEEE Photonics Technology Lett., vol. 18, no. 15, pp. 1600-1602, 2006.

106

C.X. Lian, X.Y. Li, and J. Liu,
``Optical Anisotropy of Wurtzite GaN on Sapphire Characterized by Spectroscopic Ellipsometry'',
Semicond. Sci. Technol., vol. 19, pp. 417-420, 2004.

107

Proc.IEDM Tech.Dig, San Francisco, CA, Dec. 2004,
0-7803-8684-1.

108

Proc.IEDM Tech.Dig, San Francisco, CA, Dec. 2005,
0-7803-9269-8.

109

S.H. Wemple, A. Jayaraman, and M. DiDomenico Jr.,
``Evidence from Pressure Experiments for Electron Scattering by the Ferroelectric Lattice Mode in ABO$_3$ Semiconductors'',
Phys.Rev.Lett., vol. 17, no. 3, pp. 142-145, 1966.

110

E.A. Avallone and T. Baumeister,
Mark's Standard Handbook for Mechanical Engineers,
McGraw-Hill, New York, 1996.

111

W.C. Young and R.G. Budynas,
Roark's Formulas for Stress and Strain,
McGraw-Hill, New York, 7th edition, 2002.

112

N.W. Ashcroft and N.D. Mermin,
Solid State Physics,
Harcourt College Publishers, 1976.

113

S.M. Sze, Ed.,
Semiconductor Devices: Pioneering Papers,
World Scientific, 1991.

114

E. Liniger, L. Gignac, C.-K. Hu, and S. Kaldor,
``In Situ Study of Void Groth Kinetics in Electroplated Cu Lines'',
J.Appl.Phys., vol. 92, no. 4, pp. 1803-1810, 2002.

115

L. Arnaud, T. Berger, and G. Reimhold,
``Evidence of Grain-Boundary Versus Interface Diffusion in Electromigration Experiments in Copper Damascene Interconnects'',
J.Appl.Phys., vol. 93, no. 1, pp. 192-204, 2003.

116

H. Watanabe,
``Statistics of Grain Boundaries in Gate poly-Si'',
in Proc. Simulation of Semiconductor Processes and Devices, Tokyo, Japan, Sept. 2005, pp. 39-42.

117

Electronic Industries Association,
``A Procedure for Executing SWEAT'',
JEP119, 1994.

118

Electronic Industries Association,
``Isothermal electromigration Test Procedure'',
JESD61, 1997.

119

J.O. Weidner,
Charakterisierung von Zuverlässigkeit von subm-$\mu$ m AlSiCu/TiN/Ti/n-Si-Kontakten bei hochbeschnleungiten Lebensdauertests,
Dissertation, Universität Hannover, 1999.

120

K. Banarjee, S.J. Souri, P. Kapur, and K.C. Saraswat,
``3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-On-Chip Integration'',
Proceedings of the IEEE, vol. 89, pp. 602-633, 2001.

121

W. Wu, S.H. Brongersma, M. Van Hove, and K. Maex,
``Influence of Surface and Grain-Boundary Scattering on the Resistivity of Copper in Reduced Dimensions'',
Appl.Phys.Lett., vol. 84, no. 15, pp. 2838-2840, 2004.

122

K. Fuchs,
``The Conductivity of Thin Metallic Films According to the Electron Theory of Metals'',
Proc. Cambridge Philosophical Society, vol. 34, pp. 100-108, 1938.

123

G.B. Alers, J. Sukamto, S. Park, G. Harm, and J. Reid,
``Containing the Finite Size Effect in Copper Lines'',
Semiconductor Intl., vol. 5, pp. 38-42, 2006.

124

E. Lee, N. Truong, B. Prater, and J. Kardokus,
``Copper Alloys and Alternative Barriers for Sub-$45$ nm Nodes'',
Semiconductor Intl., vol. 7, pp. 1-8, 2006.

125

E.H. Sondheimer,
``The Influence of a Transverse Magnetic Field on the Conductivity of Thin Metallic Films'',
Phys. Rev., vol. 80, pp. 401-406, 1950.

126

J.C. Anderson,
The Use of Thin Films in Physical Investigations,
Academic Press, 1966.

127

R.B. Fair,
Rapid Thermal Processing: Science and Technology,
Academic Press, 1993.

128

G. Schindler,
``Mechanical Weakness of Barrier Layers With Respect to Electro-Migration in Copper'',
Priv.Comm., 2005.

129

J. Koike and M. Wada,
``Self-Forming Diffusion Barrier Layer in Cu-Mn Alloy Metallization'',
Appl.Phys.Lett., vol. 87, no. 4, pp. 041911, 2005.

130

T. Usui, H. Nasu, J. Koike, M. Wada, S. Takahashi, N. Shimizu, T. Nishikawa, A. Yoshimaru, and H. Shibata,
``Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSi$_x$ O$_y$ Barrier Layer'',
in 2005. Proceedings of the IEEE 2005 International Interconnect Technology Conference, San Francisco, CA, June 2005, pp. 188-190,
0-7803-8752-X.

131

L.H. van Vlack,
Elements of Materials Science and Engineering,
Addison-Wesley, 1985.

132

G.S. Brady, H.R. Clauser, and J.A. Vaccari,
Materials Handbook,
McGraw-Hill, 14 $^{\mathrm{th}}$ edition, 1997.

133

M. Bauccio,
ASM Engineering Materials Reference Book,
ASM International, 2 $^{\mathrm{nd}}$ edition, 1994.

134

E.P. DeGarmo, J.T. Black, and R.A. Kohser,
Materials and Processes in Manufacturing,
Prentice Hall, 8 $^{\mathrm{th}}$ edition, 1997.

135

K.G. Budinski and M.K. Budinski,
Engineering Materials: Properties and Selection,
Prentice Hall, 6 $^{\mathrm{th}}$ edition, 1999.

136

C.J. Glassbrenner and G.A. Slack,
``Thermal Conductivity of Silicon and Germanium from 3$^{\circ}$ K to the Melting Point'',
Physical Review, vol. 134, no. 4A, pp. A1058-A1069, May 1964.

137

A.D. McConnell, S. Uma, and K.E. Goodson,
``Thermal Conductivity of Doped Polysilicon Layers'',
in Proc. of the Intl. Conference on Heat Transfer and Transport Phenomena in Microscale Structures, G.P. Celata et al., Ed., New York, 2000, pp. 413-419, Begell House.

138

S. Uma, A.D. McConnel, M. Asheghi, K. Kurabayashi, and K.E. Goodson,
``Temperature-Dependent Thermal Conductivity of Undoped Polycrystalline Silicon Layers'',
International Journal of Thermophysics, vol. 22, no. 2, pp. 605-616, 2001.

139

R.P. Gupta,
``Theory of Electromigration in Noble and Transition Metals'',
Physical Review B, vol. 25, no. 8, pp. 5188-5196, 1982.

140

G. Fasching,
Werkstoffe für die Elektrotechnik,
Springer, Wien, 1987,
2. Auflage.

141

A. Wymyslowski, K. Friedel, J. Felba, and T. Falta,
``An Experimental-Numerical Approach to Thermal Contact Resistance'',
in 9th Intl. Workshop an THERMal INvestigations of ICs and Systems [352], pp. 161-172,
0-7803-7999-3.

142

N.F. Mott and H. Jones,
The Theory of the Properties of Metals and Alloys,
Dover Publications, Inc, New York, 1958.

143

S.P. Murarka,
Silicides for VLSI Applications,
Academic Press, 1983.

144

Ed. R.A. Levy,
Reduced Thermal Processing for VLSI,
Plemum Press, New York, 1989.

145

F.Y. Huang, J.X. Lu, D.M. Jiang, X.C. Wang, and N. Jiang,
``A Novel Analytical Approach to Parameter Extraction for On-Chip Spiral Inductors Taking Into Account High-Order Parasitic Effects'',
Solid-State Electronics, vol. 50, no. 9-10, pp. 1557-1562, 2006.

146

Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu,
``Impact of On-Chip Interconnect Frequency-Dependent R(f)L(f) on Digital and RF Design'',
IEEE Trans. VLSI Systems, vol. 13, no. 1, pp. 158-162, 2005.

147

U.S. Ghoshal and L.N. Smith,
``Skin Effects in narrow Copper Microstrips at 77K'',
IEEE Trans. Mircowave Theory and Techniques, vol. 35, no. 12, pp. 1788-1795, 1988.

148

J. Noguchi, T. Oshima, U. Tanaka, H. Aoki, K. Sato, K. Ishikawa, T. Saito, N. Konishi, S. Hotta, S. Uno, and K. Kikushima,
``Integration and Reliability Issues of Cu/SiOC Interconnect for ArF/90nm Node SoC Manufacturing'',
in Proc.IEDM Tech.Dig, San Francisco, CA, Dec. 2004, pp. 527-530,
0-7803-7873-3.

149

W.F.A. Besling, V. Arnal, J.F. Guillaumond, C. Guedj, M. Broekaart, L. L. Chapelon, A. Farcy, L. Arnaud, and J. Torres,
``Integration of ALD TaN Barriers in Porous Low-k Interconnect for the 45 nm Node and Beyond; Solution to Relax Electron Scattering Effect'',
in Proc.IEDM Tech.Dig [107], pp. 325-328,
0-7803-8684-1.

150

R. Fox, O. Hinsinger, E. Richard, E. Sabouret, T. Berger, C. Goldberg, A. Humbert, G. Imbert, P. Brun, E. Ollier, C. Maurice, M. Guillermet, C. Monget, V. Plantier, H. Bono, M. Zaleski, M. Mellier, J.-P. Jacquemin, J. Flake, B.G. Sharma, L. Broussous, A. Farcy, V. Arnal, R. Gonella, S. Maubert, V. Girault, P. Vannier, D. Reber, A. Schussler, J. Mueller, and W. Besling,
``High Performance k=2.5 ULK Backend Solution Using an Improved TFHM Architecture, Extendible to the 45 nm Technology Node'',
in Proc.IEDM Tech.Dig [108], pp. 81-84,
0-7803-9269-8.

151

P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S-H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, and M. Bohr,
``A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Interconnect Layers, Low-k ILD and 0.57$\mu$ m$^2$ SRAM Cell'',
in Proc.IEDM Tech.Dig [107], pp. 657-660,
0-7803-8684-1.

152

M. Abe, M. Tada, H. Ohtake, N. Furutake, M. Narihiro, K. Arai, T. Takeuchi1, S. Saito, T. Taiji, K. Motoyama, Y. Kasama, K. Arita, F. Ito, H. Yamamoto, M. Tagami, T. Tonegawa, Y. Tsuchiya, K. Fujii, N. Oda, M. Sekine, and Y. Hayashi,
``A Robust 45 nm-node, Dual Damascene Interconnects with High Quality Cu/barrier Interface by a Novel Oxygen Absorption Process'',
in Proc.IEDM Tech.Dig [108], pp. 77-80,
0-7803-9269-8.

153

H. Geisler, H. Prinz, I. Zienert, J. Rinderknecht, M. Kiene, and E. Zschech,
``Temperatur-Dependent Stress Measurements at Inlaid Copper Interconnect Lines'',
in Zschech et al. [353], pp. 277-287.

154

S. Bothra,
``Air Gap Dielectric in Self-Aligned Via Structures'', U.S. Patent US06281585,
filed November 11, 1999; issued August 28, 2001.

155

M. Ben-Tzur, K. Ramkumar, C.A. Seams, and T.J. Rodgers,
``Low-k Dielectric Layer With Air Gaps'', U.S. Patent US06903002,
filed September 11, 2002; issued June 7, 2005.

156

S. Nitta, S. Purushothaman, S. Smith, M. Krishnan, D. Canapen, T. Dalton, W. Volksen, R.D. Miller, B. Herbst, C.K. Hu, E. Liniger, J. Lloyd, M. Lane, D.L. Rath, M. Colbum, and L. Gignac,
``Successful Dual Damascene Integration of Extreme Low k Materials (k$<$ 2.0) Using a Novel Gap Fill Based Integration Scheme'',
in Proc.IEDM Tech.Dig [107], pp. 321-324,
0-7803-8684-1.

157

G. Wiederhirn, T.J. Balk, G. Dehn J. Nucci, G. Richter, and E.Arzt,
``Passivation Effects in Copper Thin Films'',
in Zschech et al. [353], pp. 185-191.

158

M.A. Meyer, M. Grafe, H.-J. Engelmann, E. Langer, and E. Zschech,
``Investigation of the Influence of the Local Microstructure of Copper Interconnects on Void Formation and Evolution during Electromigration Testing'',
in Zschech et al. [353], pp. 175-184.

159

M. Nopper,
``Copper and More!'',
6. Dresdner Sommerschule Mikroelektronik, pp. 233-247, 2005.

160

A. Wirth,
``Electroless NiMoP Films as Capping Layers for Copper Interconnects'',
in Semicon 2005, Munich, Germany, Mar. 2005.

161

W. Fan and X.-G. Gong,
``Superheated Melting of Grain Boundaries'',
Physical Review B, vol. 72, no. 6, pp. 064121, 2005.

162

A.D. McConnell, S. Uma, and K.E. Goodson,
``Conductivity of Doped Polysilicon Layers'',
Micromechanical Systems, vol. 10, no. 3, pp. 360-369, 2001.

163

P.G. Shewmon,
Transformations in Metals,
McGraw-Hill, 1969.

164

V. Shukharev,
``Simulation of Microstructure Influence on EM-Induced Degradation in Cu Interconnects'',
in Zschech et al. [353], pp. 244-253.

165

A. Sheikholeslami,
Topography Simulation of Deposition and Etching Processes,
Dissertation, Technische Universität Wien, 2006,
http://www.iue.tuwien.ac.at/phd/sheikholeslami.

166

H. Puchner,
Advanced Process Modeling for VLSI Technology,
Dissertation, Technische Universität Wien, 1996,
http://www.iue.tuwien.ac.at/phd/puchner.

167

A. Hössinger,
Simulation of Ion Implantation for ULSI Technology,
Dissertation, Technische Universität Wien, 2000,
http://www.iue.tuwien.ac.at/phd/hoessinger.

168

D. Tamboli, S. Chang, M. Evans, I. Butcher, Q. Arefeen, M. Waddell, and S. Hymes,
``Electrochemical Processes in Metal Planarization Technologies'',
in ECS 2002-201 [354], pp. 114-125.

169

A.S. Lawing,
``Polish Rate, Pad surface Morphology and Pad Conditioning in Oxide Chemical Mechanical Polishing'',
in ECS 2002-201 [354], pp. 46-60.

170

S.M. Sze,
Semiconductor Devices Physics and Technology,
John Wiley & Sons, 2002.

171

T.S. Cale, T.P. Merchant, L.J. Borucki, and A.H. Labun,
``Topography Simulation for the Virtual Wafer Fab'',
Thin Solid Films, vol. 365, no. 2, pp. 152-175, Apr. 2000.

172

W. Pyka,
Feature Scale Modeling for Etching and Deposition Processes in Semiconductor Manufacturing,
Dissertation, Technische Universität Wien, 2000,

http://www.iue.tuwien.ac.at/phd/pyka.

173

A. Sherman,
Chemical Vapor Deposition for Microelectronics,
Noyes Publications, Park Ridge, New Jersey, 1987.

174

S. Osher and J.A. Sethian,
``Fronts Propagating with Curvature Dependent Speed: Algorithm Based on Hamilton-Jacobi Formulation'',
J.Comput.Phys., vol. 28, pp. 907-922, 1991.

175

H. Liao and T.S. Cale,
``Low-Knudsen-Number Transport and Deposition'',
J. Vac. Sci. Technol. A, vol. 12, no. 4, pp. 1020-1026, 1994.

176

S. Arrhenius,
``On the Influence of Carbonic Acid in the Air Upon the Temperature of the Ground'',
The London, Edinburgh and Dublin Philosophical Magazine and Journal of Science, vol. 5, pp. 237-276, 1896.

177

Z. Yu, B. Riccó, and R.W. Dutton,
``A Comprehensive Analytical and Numerical Model of Polysilicon Emitter Contacts in Bipolar Transistors'',
IEEE Trans.Electron Devices, vol. 31, no. 6, pp. 773-784, 1984.

178

M.M. Mandurah, K.C. Saraswat, and C.R. Helms,
``Dopant Segregation in Polycrystalline Silicon'',
J.Appl.Phys., vol. 51, no. 11, pp. 5755-5763, 1980.

179

M.M. Mandurah, K.C. Saraswat, and T.I. Kamins,
``A Model for Conduction in Polycrystalline Silicon-Part I: Theory'',
IEEE Trans.Electron Devices, vol. 28, no. 10, pp. 1163-1171, 1981.

180

M.M. Mandurah, K.C. Saraswat, and T.I. Kamins,
``A Model for Conduction in Polycrystalline Silicon-Part I: Comparison of Theory and Experiments'',
IEEE Trans.Electron Devices, vol. 28, no. 10, pp. 1171-1176, 1981.

181

J.Y. W. Seto,
``The Electrical Properties of Polycrystalline Silicon Thimn Films'',
J.Appl.Phys., vol. 42, no. 12, pp. 5247-5254, 1975.

182

C.M. Osburn, I. Kim, S.K. Han, I. De, K.F. Yee, S. Gannavaram, S.J. Lee, C.-H. Lee, Z.J. Luo, W. Zhu, J. R. Hauser, D.-L. Kwong, G. Lucovsky, T.P. Ma, and M.C. Öztürk,
``Vertically Scaled MOSFET Gate Stacks and Junctions: How Far are we Likely to Go?'',
IBM J.Res.Dev., vol. 46, no. 2/3, pp. 299-315, 2002.

183

H.-S.P. Wong,
``Beyond the Conventional Transistor'',
IBM J.Res.Dev., vol. 46, no. 2/3, pp. 133-168, 2002.

184

M. LeRoy, E. Lheurette, O. Vanbesien, and D. Lippens,
``Wave-Mechanical Calculations of Leakage Current Through Stacked Dielectrics for nanotransistor Metal-Oxide-Semiconductor Design'',
J.Appl.Phys., vol. 93, no. 5, pp. 2966-2971, 2003.

185

G.D. Wilk, R.M. Wallace, and J.M. Anthony,
``High-k Gate Dielectrics: Current Status and Materials Properties Considerations'',
J.Appl.Phys., vol. 89, no. 10, pp. 5243-5275, 2001.

186

J. Robertson,
``Band Offsets of Wide-Bandgap Oxides and Implications for Future Electronic Devices'',
J.Vac.Sci.Technol., vol. 18, no. 3, pp. 1785-1791, 2000.

187

T. Hori, Y. Naito, H. Iwasaki, and H. Esaki,
``Interface States and Fixed Charges in Nanometer-Range Thin Nitrided Oxides Prepared by Rapid Thermal Annealing'',
IEEE Electron Device Lett., vol. 7, no. 12, pp. 669-671, 1986.

188

T. Hori, H. Iwasaki, Y. Naito, and H. Esaki,
``Electrical Nitrided and Physical Characteristics of Thin Oxides Prepared by Rapid Thermal Nitridation'',
IEEE Trans.Electron Devices, vol. 34, no. 11, pp. 2238-2244, 1987.

189

J. Zhang, J.S. Yuan, Y. Ma, and A.S. Oates,
``Design Optimization of Stacked Layer Dielectrics for Minimum Gate Leakage Currents'',
Solid-State Electron., vol. 44, no. 12, pp. 2165-2170, 2000.

190

J.D. Casperson, L.D. Bell, and H.A. Atwater,
``Materials Issues for Layered Tunnel Barrier Structures'',
J.Appl.Phys., vol. 92, no. 1, pp. 261-267, 2002.

191

M. von Arx, O. Paul, and H. Baltes,
``Process-Dependent Thin Film Thermal Conductivities for Thermal CMOS MEMS'',
Microelectromechanical Systems, vol. 9, no. 1, pp. 136-145, Mar. 2000.

192

F. Völklein and H. Baltes,
``A Microstructure for Measurement of Thermal Conductivity of Polycrystalline Thin Films'',
Microelectromechanical Systems, vol. 1, no. 4, pp. 193-196, 1992.

193

N.R. Swart,
Heat Transport in Thermal-Based Microsensors,
Dissertation, University of Waterloo, 1994.

194

O. Paul, M. von Arx, and H. Baltes,
``Process-Dependent Thermophysical Properties of CMOS IC Thin Films'',
in Digest of Technical Papers, vol. 1, Transducers '95,, Stockholm, Sweden, 1995, pp. 178-181.

195

Y.C. Tai, C.H. Mastrangelo, and R.S. Müller,
``Thermal Conductivity of Heavily Doped LPCVD Polycrystalline Silicon Films'',
J.Appl.Phys., vol. 63, no. 5, pp. 1442-1447, 1988.

196

C.H. Shomate,
``A Method for Evaluating and Correlating Thermodynamic Data'',
J.Phys.Chem, vol. 58, no. 4, pp. 368-372, 1954.

197

A. Cezairliyan,
Specific Heat of Solids,
Hemisphere Publishing Corp., 1988.

198

L.K. Nash,
Elements of Chemical Thermodynamics,
Dover Publications, Inc., Mineola, New York, 2nd edition, 2005.

199

K. Yamaguchi and K. Itakagi,
``Measurement of High Temperature Heat Content of Silicon by Drop Calorimetry'',
J.Thermal.Anal.Cal., vol. 69, pp. 1059-1066, 2002.

200

G. Wang, X. Zhang, and P.S. Ho,
``Chip-Packaging Interaction and Reliability Impact on Cu/Low k Interconnects'',
in Zschech et al. [353], pp. 73-82.

201

C.H. Pan and C.L. Tung,
``A Simple Method for Determination of Thermal Conductivity Coefficients of Dielectric Films'',
in Proc. 2001 Intl. Symposium Micromechatronics and Human Science, Nagoya, Japan, 2001, pp. 109-116.

202

C. Kittel,
Introduction to Solid State Physics,
Wiley, 7th edition, 1996.

203

J. Hoekstra, A.P. Sutton, T.N. Todorov, and A.P. Horsfield,
``Electromigration of Vacancies in Copper'',
Physical Review B, vol. 62, no. 13, pp. 8568-8571, 2000.

204

M.J. Aziz, P.C. Sabin, and G.-Q. Lu,
``The Activation Strain Tensor: Nonhydrostatic Stress Effects on Crystall-Growth Kinetics'',
Physical Review A, vol. 44, no. 18, pp. 9812-9816, 1991.

205

P. Pichler,
Intrinsic Point Defects, Impurities, and Their Diffusion in Silicon,
Springer, Wien, NewYork, 2004.

206

H.B. Huntington and A.R. Grone,
``Current-Induced Marker Motion in Gold Wires'',
J.Phys.Chem.Solids, vol. 20, no. 1-2, pp. 76-87, 1961.

207

M. Karpovski A. Gladkikh, A. Palevski, and Y.S. Kaganovski,
``Effect of Microstructure on Electromigration Kinetics in Cu Lines'',
J.Phys.D: Appl.Phys., vol. 31, no. 14, pp. 1626-1629, 1998.

208

R. Kircheim,
``Stress and Electromigration in Al-Lines of Integrated Circuits'',
Acta Metallurg. et Mater., vol. 40, no. 2, pp. 309-323, 1992.

209

J.R. Lloyd, C.E. Murray, T.M. Shaw, M.W. Lane, X.-H. Liu, and E.G. Liniger,
``Theory for Electromigration Failure in Cu Conductors'',
in Zschech et al. [353], pp. 23-24.

210

E.T. Ogawa, K.D. Lee, V.A. Blaschke, and P.S. Ho,
``Electromigration Reliability Issues in Dual-Damascene Cu Interconnects'',
IEEE Trans.Reliability, vol. 51, no. 4, pp. 403-419, 2002.

211

J.R. Lloyd, J. Clemens, and R. Snede,
``Copper Metalization Reliability'',
Microelectron.Reliab., vol. 39, no. 11, pp. 1595-1602, 1999.

212

O. Pierre-Louis and T.L. Einstein,
``Electromigration of Single-Layer Clusters'',
Physical Review B, vol. 62, no. 20, pp. 1829-1838, 2000.

213

M. Hauschildt, M. Gall, S. Thrasher, P. Justison, L. Michaelson, R. Hernandez, H. Kawasaki, and P.S. Ho,
``Statistical Analysis of Electromigration Lifetimes for Cu Interconnects'',
in Zschech et al. [353], pp. 164-174.

214

Z.H. Gan, W. Shao, M.Y. Yan, A.V. Vairagar, T. Zaporozhets, M.A. Meyer, A. Krishnamoorthy, K.N. Tu, A. Gusak, E. Zschech, and S.G. Mhaisalkar,
``Understanding the Impact of Surface Engineering, Structure, and Design on Electromigration through Monte Carlo Simulation and In-Situ SEM Studies'',
in Zschech et al. [353], pp. 34-42.

215

J.R. Black,
``Electromigration - A Brief Survey and Some Results'',
IEEE Trans.Electron Devices, vol. 16, no. 4, pp. 338-347, 1969.

216

J.R. Black,
``Electromigration Failure Modes in Aluminum Mateallization for Semiconductor Devices'',
Proceeding fo the IEEE, vol. 57, pp. 1587-1693, 1969.

217

D. Dalleau and K. Weide-Zaage,
``Three-Dimensional Voids Simulation in Chip Metallization Structures: A Contribution to Reliability Evaluation'',
Microelectron. Reliab., vol. 41, no. 9-10, pp. 1625-1630, 2001.

218

C.F. Gauß,
``Zur Paralellentheorie. Brief an Taurinus, 8. November 1824'',
Werke, Bd. 8: Arithmetik und Algebra: Nachträge zu Band 1-3, pp. 186-188, 1863.

219

C. Großmann and J. Terno,
Numerik der Optimierung,
B. G. Teubner, Stuttgart, Germany, 1997.

220

E.G. Birgin, J.S. Martínez, and M. Raydan,
``Algorithm 813: SPG--Software for Convex-Constrained Optimization'',
ACM Transactions on Mathematical Software, vol. 27, no. 3, pp. 340-349, 2001.

221

R. Fletcher,
``Am Ideal Penalty Function for Constrained Optimization'',
J.Inst.Math.Appl., vol. 15, pp. 319-342, 1975.

222

R. Fletcher,
Practical Optimization Methods,
Wiley, 2nd edition, 1987.

223

D.P. Bertsekas,
``Necessary and Sufficient Conditions for a Penalty Method to be Exact'',
Math.Programming, vol. 9, pp. 87-99, 1975.

224

A.V. Fiacco and G.P. McCormick,
Nonlinear Programming: Sequential Unconstrained Minimization Techniques,
Wiley, 1968.

225

E.J. Beltrani,
An Alogrithmic Approach to Nonlinear Analysis and Optimization,
Academic Press, 1970.

226

K.F. Frisch,
The Logarithmic Potential Method of Convex Programming,
Memorandum of May 13, University Institute of Economics, Oslo, 1955.

227

L. Bittner,
``Eine Verallgemeinerung des Verfahrens des logarithmischen Potentials von Frisch für nicht lineare Optimierungsaufgaben'',
in Colloqu. on applic.math.to econ., 1965, pp. 43-53.

228

F.A. Lootsma,
Boundary Properties of Penalty Functions for Constrained Minimization,
Philips Res.Rept.Suppl., 3, 1970.

229

C. Großmann and A.A. Kaplan,
Strafmethoden und modifizierte Lagrange-Funktionen in der nichtlinearen Optimierung,
Teubner, 1979.

230

C.T. Kelley,
Iterative Methods for Optimization,
SIAM, Philadelphia, 1999.

231

Yu. Ermoliev and R.J.-B. Wets, Eds.,
Numerical Techniques for Stochastic Optimization, vol. 10 of Springer Series in Computational Mathematics,
Springer, 1988.

232

Y. Censor and S.A. Zenios,
Parallel Optimization: Theory, Algorithms, and Applications,
Oxford University Press, Oxford, 1997.

233

P.E. Gill, W. Murray, and M.H. Wright,
Practical Optimization,
Academic Press, 1995.

234

P. Lloyd, C.C. McAndrew, M.J. McLennan, S. Nassif, K. Singhal, Ku. Singhal, P.M. Zeitzoff, M.N. Darwish, K. Haruta, J.L. Lentz, H. Vuong, M.R. Pinto, C.S. Rafferty, and I.C. Kizilyalli,
``Technology CAD at AT&T'',
in Technology CAD Systems, F. Fasching, S. Halama, and S. Selberherr, Eds., Wien, 1993, pp. 1-24, Springer.

235

R. Minixhofer,
Integration Technology Simulation into the Semiconductor Manufacturing Environment,
Dissertation, Technische Universität Wien, 2006,

http://www.iue.tuwien.ac.at/phd/minixhofer.

236

T.G. Kolda, R.M. Lewis, and V. Torczon,
``Optimization by Direct Search:New Perspectives on some Classical and Modern Methods'',
SIAM Review, vol. 45, no. 3, pp. 385-482, 2003.

237

G.E.P. Box and K.B. Wilson,
``On the Experimental Attainment of Optimum Conditions'',
Journal of the Royal Statistical Society Series B, vol. 13, no. 1, pp. 1-45, 1951.

238

D.S. Boning and P.K. Mozumder,
``DOE/Opt: A System for Design of Experiments, Response Surface Modeling, and Optimization Using Process and Device Simulation'',
IEEE Trans.Semiconductor Manufacturing, vol. 7, no. 2, pp. 233-244, 1994.

239

Ch. Pichler, N. Khalil, G. Schrom, and S. Selberherr,
``TCAD Optimization Based on Task-Level Framework Services'',
in Simulation of Semiconductor Devices and Processes, H. Ryssel and P. Pichler, Eds., Wien, Austria, 1995, vol. 6, pp. 70-73, Springer.

240

R. Cartuyvels, R. Booth, S. Kubicek, L. Dupas, and K.M. De Meyer,
``A Powerful TCAD System Including Advanced RSM Techniques for Various Engineering Optimization Problems'',
in Simulation of Semiconductor Devices and Processes, S. Selberherr, H. Stippel, and E. Strasser, Eds., Wien, 1993, vol. 5, pp. 29-32, Springer.

241

V. Senez, T. Hoffmann, and A. Tixier,
``Calibration of a Two-Dimensional Numerical Model for the Optimization of LOCOS-Type Isolations by Response Surface Methodology'',
IEEE Trans.Semiconductor Manufacturing, vol. 13, no. 4, pp. 416-426, Nov. 2000.

242

D.W. Marquardt,
``An Algorithm for the Estimation of Nonlinear Parameters'',
J. Soc. Ind. Appl. Maths., vol. 11, pp. 431-441, 1963.

243

C. Heitzinger,
Simulation and Inverse Modeling of Semiconductor Manufacturing Processes,
Dissertation, Technische Universität Wien, 2002,
http://www.iue.tuwien.ac.at/phd/heitzinger.

244

R. Pfeifer,
Effektive Messauswertung mit der Gauß'schen Fehlerquadratmethode,
Sport und Buch Strauß, 2001.

245

J.J. Moré, B.S. Garbow, and K.E. Hillstrom,
``Users Guide for MINPACK-1'', 1980,
Argonne National Laboratory Report ANL-80-74, Argone, IL.

246

J.J. Moré, D.C. Sorensen, K.E. Hillstrom, and B.S. Garbow,
The MINPACK Project,
Sources and Development of Mathematical Software. Prentice-Hall, Englewood Clifs, NJ, 1984.

247

2nd Intl. Conf. on Modeling and Simulation of Microsystems, San Juan, Puerto Rico, USA, Apr. 1999.

248

R. Strasser,
Rigorous TCAD Investigations on Semiconductor Fabrication Technology,
Dissertation, Technische Universität Wien, 1999,
http://www.iue.tuwien.ac.at/phd/strasser.

249

P. Spellucci,
Donlp2 Users Guide,
NetLib Project, 1995.

250

P. Spellucci,
``An SQP Method For General Nonlinear Programs Using Only Equality Constrained Subproblems'',
Mathematical Programming, vol. 82, no. 3, pp. 413-448, 1998.

251

G.H. Golub and C.F. Van Loan,
Matrix Computations,
John Hopkins University Press, second edition, 1989.

252

G.H. Golub and D.P. O'Leary,
``Some History of the Conjugate Gradient and Lanczos Algorithms: 1948-1976'',
SIAM Review, vol. 31, no. 1, pp. 50-102, 1989.

253

M.R. Field,
``Optimizing a Parallel Conjugate Gradient Solver'',
SIAM J.Sci.Comput., vol. 19, no. 1, pp. 27-37, 1998,
http://www.siam.org/journals/sisc/19-1/30220.html.

254

P. Concus and G.H. Golub,
``A Generalized Conjugate Gradient Method for Nonsymmetric Systems of Linear Equations'',
in Proc. 2nd Int.Symp. on Computing Methods in Applied Sciences and Engineering, R. Glowinski and J.L. Lions, Eds., Berlin, 1976, vol. 134 of Lecture Notes in Economics and Mathematical Systems, pp. 56-65, Springer.

255

H.A. van der Vorst,
``BI-CGSTAB: A Fast and Smoothly Converging Variant of BI-CG for the Solution of Nonsymmetric Linear Systems'',
SIAM J.Sci.Stat.Comput., vol. 13, no. 2, pp. 631-644, 1992.

256

P. Sonneveld,
``CGS, A Fast Lanczos-Type Solver for Nonsymmetric Linear Systems'',
SIAM J.Sci.Stat.Comput., vol. 10, no. 1, pp. 36-52, 1989.

257

J. Gablonsky,
``An Implementation of the DIRECT Algorithm'',
Tech. Rep., Department of Mathematics, North Carolina State University, 1998,

http://www4.ncsu.edu/eos/users/c/ctkelley/www/optimization_codes.html.

258

M. Björkman and K. Holström,
``Global Optimization Using the DIRECT Algorithm in Matlab'',
AMO - Advanced Modeling and Optimization, vol. 1, no. 2, pp. 17-37, 1999.

259

J. Holland,
``Adaption in Natural and Artificial Systems'',
University of Michigan Press, Ann Arbor, MI, 1975.

260

D.E. Goldberg,
Genetic Algorithms in Search and Optimization,
Addison-Wesley, 1989.

261

Z. Michalewicz,
Genetic Algorithms + Data Structures = Evolution Programs,
Springer, Berlin, 1996.

262

M. Wall,
``GAlib A C++ Library of Genetic Algorithm Components'',
Massachusetts Institute of Technology, 2000,
http://lancet.mit.edu/ga.

263

T. Binder,
Rigorous Integration of Semiconductor Process and Device Simulators,
Dissertation, Technische Universität Wien, 2002,
http://www.iue.tuwien.ac.at/phd/binder.

264

R.C. Eberhardt and J. Kennedy,
``A New Optimizer Using Particle Swarm Theory'',
in Proceedings of the Sixth International Symposium on Micromachine and Human Science, Nagoya, Japan, 1995, pp. 39-45.

265

J. Kennedy and R.C. Eberhardt,
``Particle Swarm Optimization'',
in Proceedings of IEEE International Conference on Neural Networks, Piscataway, NJ., 1995, pp. 1942-1948.

266

M. Clerc,
``Discrete Particle Swarm Optimization'', New Optimization Techniques in Engineering,
Springer, 2004.

267

F. van den Bergh,
An Analysis of Particle Swarm Optimizers,
Phd thesis, Department of Computer Science, University of Pretoria, 2002.

268

F. van den Bergh and A.P. Engelbrecht,
``A Cooperative Approach to Particle Swarm Optimisation'',
IEEE Transactions on Evolutionary Computation, vol. 8, no. 3, pp. 225-239, 2004.

269

F. Chang and D. Xue,
``Optimal Concurrent Design Based Upon Distributed Product Development Life-Cycle Modeling'',
Robotics and Computer-Integrated Manufacturing, vol. 17, no. 6, pp. 469-486, 2001.

270

M. Clerc and J. Kennedy,
``The Particle Swarm-Explosion, Stability, and Convergence in a Multidimensional Complex Space'',
IEEE Transactions on Evolutionary Computation, vol. 6, no. 1, pp. 58-73, 2002.

271

N. Metropolis, A.W. Rosenbluth, M.N. Rosenbluth, and A. H. Teller,
``Equation of State Calculations by Fast Computing Machines'',
The Journal of Chemical Physics, vol. 21, no. 6, June 1953.

272

S. Kirkpatrick, C.D. Gelatt, and M.P. Vecchi,
``Optimization by Simulated Annealing'',
Science, vol. 220, no. 4598, pp. 671-680, 1983.

273

S. Kirkpatrick,
``Optimization by Simulated Annealing: Quantitative Studies'',
J.Stat.Phys., vol. 34, pp. 975-986, 1984.

274

D. Kirkpatrick,
``Optimal Search in Planar Subdivisions'',
SIAM J.Computing, vol. 12, no. 1, pp. 28-35, 1983.

275

L. Ingber,
``Very Fast Simulated Re-Annealing'',
Mathematical Computer Modelling, vol. 12, pp. 967-973, 1989,
http://www.ingber.com/asa89_vfsr.ps.gz.

276

L. Ingber,
``Genetic Algorithms and Very Fast Simulated Re-Annealing: A Comparision'',
Mathematical and Computer Modelling, vol. 16, pp. 87-100, 1992,

http://www.ingber.com/asa92_saga.ps.gz.

277

V. Cerny,
``Thermodynamical Approach to the Traveling Salesman Problem: an Efficient Simulation Algorithm'',
J. Opt. Theory Appl., vol. 45, pp. 41-45, 1985.

278

N. Metropolis and S. Ulam,
``The Monte Carlo Method'',
Journal of the American Statistical Association, vol. 44, no. 247, pp. 335-341, 1949.

279

A. Abramo, L. Baudry, R. Brunetti, R. Castagne, M. Charef, F. Dessenne, P. Dollfus, R. Dutton, W.L. Engl, R. Fauquembergue, C. Fiegna, M.V. Fischetti, S. Galdin, N. Goldsman, M. Hackel, C. Hamaguchi, K. Hess, K. Hennacy, P. Hesto, J.M. Higman, T. Iizuka, C. Jungemann, Y. Kamakura, H. Kosina, T. Kunikiyo, S.E. Laux, H. Lin, C. Maziar, H. Mizuno, H.J. Peifer, S. Ramaswamy, N. Sano, P.G. Scrobohaci, S. Selberherr, M. Takenaka, T.-W. Tang, K. Taniguchi, J.L. Thobel, R. Thoma, K. Tomizawa, M. Tomizawa, T. Vogelsang, S.-L. Wang, X. Wang, C.-S. Yao, P.D. Yoder, and A. Yoshii,
``A Comparison of Numerical Solutions of the Boltzmann Transport Equation for High-Energy Electron Transport Silicon'',
IEEE Trans.Electron Devices, vol. 41, no. 9, pp. 1646-1654, 1994.

280

S. Wagner, V. Palankovski, T. Grasser, G. Röhrer, and S. Selberherr,
``Direct Extraction Feature for Scattering Parameters of SiGe-HBTs'',
Applied Surface Science, vol. 224, no. 1-4, pp. 365-369, 2004.

281

M. Wagner, G. Span, S. Holzer, V. Palankovski, O. Triebl, and T. Grasser,
``Power Output Improvement of SiGe Thermoelectric Generators'',
ECS Transactions: SiGe and Ge: Materials, Processing, and Devices, vol. 3, no. 7, pp. 1151-1162, 2006.

282

T. Binder, C. Heitzinger, and S. Selberherr,
``A Qualitative Study on Global and Local Optimization Techniques for TCAD Analysis Tasks'',
in Proc. Modeling and Simulation of Microsystems (MSM 2001), Hilton Head Island, South Carolina, USA, Mar. 2001, pp. 466-469.

283

M. Burger and R. Pinnau,
``Fast Optimal Design of Semiconductor Devices'',
SIAM J.Appl.Math., vol. 64, no. 1, pp. 108-126, 2003.

284

T.J. Lorenzen and V.L. Anderson,
Design of Experiments,
Marcel Dekker, New York, 1991.

285

J.J. Moré and S.J. Wright,
Optimization Software Guide, vol. 14 of Frontiers in Applied Mathematics,
SIAM, Philadelphia, 1993.

286

P. Fleischmann, E. Leitner, and S. Selberherr,
``Optimized Geometry Preprocessing for Three-Dimensional Semiconductor Process Simulation'',
in Intl. Conf. on Applied Modelling and Simulation [355], pp. 317-321.

287

D.M. Betz,
XLISP: An Object-Oriented Lisp, Version 2.1,
Apple, Peterborough, New Hampshire, USA, 1989.

288

P.H. Winston and B.K.P. Horn,
Lisp,
Addison-Wesley, 1989.

289

Institut für Mikroelektronik, Technische Universität Wien, Austria,
VISTA Documentation 1.3-1, VLISP Manual, Jan. 1996.

290

Python Software Foundation,
Python, Jan. 2005.

291

S. Wagner,
Small-Signal Device and Circuit Simulation,
Dissertation, Technische Universität Wien, 2005,
http://www.ue.tuwien.ac.at/phd/wagner.

292

M. Stockinger,
Optimization of Ultra-Low-Power CMOS Transistors,
Dissertation, Technische Universität Wien, 1999,
http://www.iue.tuwien.ac.at/phd/stockinger.

293

H. Herold,
Das Qt Buch,
SuSE-Press, 2001.

294

Z. Yang and K. Duddy,
``CORBA: A Platform for Distributed Object Computing (A State-of-the-Art Report on OMG/CORBA)'',
ACM Operating System Review, vol. 30, no. 2, pp. 4-31, Apr. 1996.

295

W. Emmerich and S. Tai, Eds.,
Engineering Distributed Objects, vol. 1999 of Lecture Notes in Computer Science,
Springer, 2001.

296

E. Al-Ani, R. Heinzl, P. Schwaha, T. Grasser, and S. Selberherr,
``Three-Dimensional State-Of-The-Art Topography Simulation'',
in The 2005 European Simulation and Modelling Conference Proceedings, Porto, Portugal, Oct. 2005, pp. 430-432.

297

Synopsys,
Taurus-Tsuprem-4 Two-Dimensional Process Simulation Program User Manual,
Synopsys, Mountain View, 2003.

298

S.E. Hansen and R. Dutton,
SUPREME-III User's Manual,
Stanford University, 1986.

299

S. E. Hansen and M. D. Deal, Eds.,
SUPREME-IV.GS Two Dimensional Process Simulation for Silicon and Gallium Arsenide,
Stanford University, 1993.

300

Inc. Technology Modeling Associates,
TMA TSUPREME-4, Two-Dimensional Process Simulation Program, Version 6.5 Users's Manual,
Technology Modeling Associates, Inc., Sunnyvale, CA, 1997.

301

R. Wittmann, A. Hössinger, and S. Selberherr,
``Improvement of the Statistical Accuracy for the Three-Dimensional Monte Carlo Simulation of Ion Implantation'',
in 15th European Simulation Symposium on Simulation in Industry, Delft, The Netherlands, Oct. 2003, pp. 35-40.

302

R. Heinzl and T. Grasser,
``Generalized Comprehensive Approach for Robust Three-Dimensional Mesh Generation for TCAD'',
in Proc. Simulation of Semiconductor Processes and Devices, Tokyo, Japan, Sept. 2005, pp. 211-214.

303

Institut für Mikroelektronik, Technische Universität Wien, Austria,
VMC 2.0 User's Guide, 2006,
http://www.iue.tuwien.ac.at/software.

304

M. Karner, S. Holzer, M. Vasicek, W. Goes, M. Wagner, H. Kosina, and S. Selberherr,
``Numerical Analysis of Gate Stacks'',
ECS Trans., vol. 3, no. 3, pp. 299-308, 2006.

305

M. Karner, E. Ungersboeck, A. Gehring, S. Holzer, H. Kosina, and S. Selberherr,
``Proc. Simulation of Semiconductor Processes and Devices'',
in Simulation of Semiconductor Processes and Devices, Monterey, CA, Sept. 2006, pp. 314-317.

306

J.R. Shewchuk,
``Triangle: Engineering a 2D Quality Mesh Generator and Delaunay Triangulator'',
in Applied Computational Geometry: Towards Geometric Engineering, M. C. Lin and D. Manocha, Eds., vol. 1148 of Lecture Notes in Computer Science, pp. 203-222. Springer-Verlag, May 1996.

307

G.L. Dirichlet,
``Über die Reduktion der positiven quadratischen Formen mit drei unbestimmten ganzen Zahlen'',
Journal für die Reine und Angewandte Mathematik, vol. 40, pp. 209-227, 1850.

308

G. Voronoi,
``Nouvelles applications des paramètres continus à la théorie des formes quadratiques'',
Journal für die Reine und Angewandte Mathematik, vol. 133, pp. 97-178, 1907.

309

B.N. Delaunay,
``Sur la Sphere Vide'',
Izvestia Akademia Nauk SSSR, VII Seria, Otdelenie Matematicheskii i Estestvennyka Nauk, vol. 7, pp. 793-800, 1934.

310

D.F. Watson,
``Computing the Delaunay Tesselation with Application to Voronoi Polytopes'',
The Computer Journal, vol. 24, no. 2, pp. 167-172, 1981.

311

W. Pyka, P. Fleischmann, B. Haindl, and S. Selberherr,
``Three-Dimensional Simulation of HPCVD--Linking Continuum Transport and Reaction Kinetics with Topography Simulation'',
IEEE Trans.Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 12, pp. 1741-1749, 1999.

312

P. Fleischmann, W. Pyka, and S. Selberherr,
``Mesh Generation for Application in Technology CAD'',
IEICE Trans.Electron., vol. E82-C, no. 6, pp. 937-947, 1999.

313

P. Fleischmann,
Mesh Generation for Technology CAD in Three Dimensions,
Dissertation, Technische Universität Wien, 2000,
http://www.iue.tuwien.ac.at/phd/fleischmann.

314

K. Kernstock,
``Ein Java GUI für den VSP'',
Tech. Rep., Institut für Mikroelektronik, Technische Universität Wien, Nov. 2006,
Internal Project Report.

315

M. Zohlhuber,
Visualisierung von Simulationsdaten,
Diplomarbeit, Technische Universität Wien, 2003.

316

T. Binder and S. Selberherr,
``Object-Oriented Wafer-State Services'',
in Proc. European Simulation Multiconference ESM 92, Ghent, Belgium, 2000, pp. 360-364.

317

S. Holzer, M. Wagner, A. Sheikholeslami, M. Karner, G. Span, T. Grasser, and S. Selberherr,
``An Extendable Multi-Purpose Simulation and Optimization Framework for Thermal Problems in TCAD Applications'',
in 12th Intl. Workshop an THERMal INvestigations of ICs and Systems, Nice, France, Sept. 2006, pp. 239-244, TIMA,
2-9161-8704-9.

318

A. Hössinger, T. Binder, W. Pyka, and S. Selberherr,
``Advanced Hybrid Cellular Based Approach for Three-Dimensional Etching and Deposition Simulation'',
in Simulation of Semiconductor Processes and Devices, Athens, Greece, Sept. 2001, pp. 424-427.

319

J. A. Sethian,
Level Set Methods and Fast Marching Methods,
Cambridge University Press, Cambridge, 1999.

320

D. Adalsteinsson and J.A. Sethian,
``A Level Set Approach to a Unified Model for Etching, Deposition, and Lithography I: Algorithms and Two-Dimensional Simulations'',
J.Comp.Phys., vol. 120, pp. 128-144, 1995.

321

D. Adalsteinsson and J.A. Sethian,
``A Level Set Approach to a Unified Model for Etching, Deposition, and Lithography II: Three-Dimensional Simulations'',
J.Comp.Phys., vol. 122, pp. 348-366, 1995.

322

D. Adalsteinsson and J.A. Sethian,
``A Level Set Approach to a Unified Model for Etching, Deposition, and Lithography III: Re-Deposition, Re-Emission, Surface Diffusion, and Complex Simulations'',
Tech. Rep., Department of Mathematics and Lawrence Berkeley Laboratory, University of California, Berkeley, California 94720, Aug. 1997.

323

J.A. Sethian and D. Adalsteinsson,
``An Overview of Level Set Methods for Etching, Deposition, and Lithography Development'',
IEEE Trans.Semiconductor Manufacturing, vol. 10, no. 1, pp. 167-184, Feb. 1997.

324

S. Osher and J.A. Sethian,
``Fronts Propagating with Curvature Dependent Speed: Algorithms Based on Hamilton-Jacobi Formulations'',
J.Comput.Phys., vol. 79, pp. 12-49, 1988.

325

J.C. Rey, J. Li, V. Boksha, D. Adalsteinsson, and J.A. Sethian,
``Topography Simulation for Interconnect Deposition'',
Solid State Technology, vol. 2, pp. 77-82, 1998.

326

T.J. Barth and J.A. Sethian,
``Numerical Schemes for the Hamilton-Jacobi and Level Set Equations on Triangulated Domains'',
Tech. Rep., Information Sciences Directorate, NASA Ames Research Center and Department of Mathematics, University of California, Berkeley, Sept. 1997.

327

D. Adalsteinsson and J.A. Sethian,
``Computational Performance of Level Set Methods for Etching, Deposition, and Lithography Development'',
in Simulation of Semiconductor Processes and Devices, Tokyo, Japan, 1996, pp. 79-80, Business Center for Academic Societies Japan.

328

T.S. Cale and G.B. Raupp,
``A Unified Line-of-Sight Model of Deposition in Rectangular Trenches'',
J.Vac.Sci.Technol.B, vol. 8, no. 6, pp. 1242-1248, 1990.

329

M.E. Coltrin, P. Ho, H.K. Moffat, and R.J. Buss,
``Chemical Kinetics in Chemical Vapor Deposition: Growth of Silicon Dioxide from Tetraethoxysilane (TEOS)'',
Thin Solid Films, vol. 365, no. 2, pp. 251-263, 2000.

330

D. Adalsteinsson and J.A. Sethian,
``Three-Dimensional Profile Evolution under Low Sticking Coefficient'',
in Simulation of Semiconductor Processes and Devices, Cambridge, Massachusetts, 1997, pp. 61-64.

331

P. McCann, K. Somasundram, S. Byrne, and A. Nevi,
``Conformal Deposition of LPCVD TEOS'',
in Micromachining and Microfabrication Process Technology VII, J.M. Karam and J.A. Yasaitis, Eds., Oct. 2001, pp. 329-340.

332

U.H. Kwon and W.J. Lee,
``Three-Dimensional Deposition Topography Simulation Based on New Combination of Flux Distribution and Surface Representaion Algorithms'',
Thin Solid Films, vol. 445, pp. 80-89, 2003.

333

C. Heitzinger, J. Fugger, O. Häberlen, and S. Selberherr,
``Simulation and Inverse Modeling of TEOS Deposition Processes Using a Fast Level Set Method'',
in Simulation of Semiconductor Processes and Devices, Kobe, Japan, Sept. 2002, pp. 191-194.

334

S. Holzer, A. Sheikoleslami, S. Wagner, C. Heitzinger, T. Grasser, and S. Selberherr,
``Optimization and Inverse Modeling for TCAD Applications'',
in Symposium on Nano Devices Technology 2004, Hsinchu, Taiwan, May 2004, pp. 113-116.

335

B. Sell, A. Sänger, G. Schulze-Icking, K. Pomplun, and W. Krautschneider,
``Chemical Vapor Deposition of Tungsten Silicide (WSix) for High Aspect Ratio Applications'',
Thin Solid Films, vol. 443, no. 1-2, pp. 97-107, 2003.

336

A. Doyle,
``A Thick Polysilicon Three-State Fuse'',
Motorola Technical Developements 3, pp. 31-32, 1993.

337

O. Kim,
``CMOS Trimming Circuit Based on Polysilicon Fusing'',
Electr.Lett., vol. 34, no. 4, pp. 355-356, 1998.

338

D.J. Nickel,
``Element Trimmable Fusible Link'',
IBM Technical Disclosure Bulletin, vol. 26, no. 8, pp. 4415, 1984.

339

J.R. Lloyd and M.R. Polcari,
``Polysilicon Fuse'',
IBM Technical Disclosure Bulletin, vol. 24, no. 7A, pp. 3442, 1981.

340

Y. Fukada, S. Kohda, K. Masuda, and Y. Kitano,
``A New Fusible-Type Programmable Element Composed of Aluminum and Polysilicon'',
IEEE Trans.Electron Devices, vol. 33, no. 2, pp. 250-253, 1986.

341

D.W. Greve,
``Programming Mechanism of Polysilicon Resistor Fuses'',
IEEE Trans.Electron Devices, vol. 29, no. 4, pp. 719-724, 1982.

342

D.W. Greve,
``Programming Mechanism of Polysilicon Fuse Links'',
IEEE Trans.Electron Devices, vol. 17, no. 2, pp. 349-354, 1982.

343

C. Vahlas, P.-Y. Chevalier, and E. Blanquet,
``A Thermodynamic Evaluation of Four Si-M (M = Mo, Ta, Ti, W) Binary Systems'',
Computer Coupling of Phase Diagrams and Thermochemistry, vol. 13, no. 3, pp. 273-292, 1989.

344

D.C. Katsis and J.D. van Wyk,
``Experimental Measurements and Simulation of Thermal Performance Due to Aging in Power Semiconductor Devices'',
in Proc. Industry Applications Conference, 2002, 37th IAS Annual Meeting, Pittsburgh, PA, 2002, pp. 1746-1751.

345

C. Hollauer,
Modelling of Thermal Oxidation and Stress Effect,
Dissertation, Technische Universität Wien, 2007,
http://www.iue.tuwien.ac.at/phd/hollauer.

346

D. Fedasyuk and V. Makar,
``Coupled Thermo-Mechanical Modeling and Optimization of Power Semiconductor Devices'',
in 9th Intl. Workshop an THERMal INvestigations of ICs and Systems [352], pp. 93-98,
0-7803-7999-3.

347

F. Kreupl, A.P. Graham, M. Liebau, G.S. Duesberg, R. Seidel, and E. Unger,
``Carbon Nanotubes for Interconnect Applications'',
in Proc.IEDM Tech.Dig [107], pp. 333-326,
0-7803-8684-1.

348

H.J. Dirschmid,
Mathematische Grundlagen der Elektrotechnik,
Vieweg, 1986.

349

National Communication System Technology & Standards Devision,
``Federal Standard 1037C: Telecommunications: Glossary of Telecommunication Terms'', 1996,
General Services Administration Information Technology Service.

350

Proc. Microtechnologies for the New Millennium 2005: VLSI Circuits and Systems, Sevilla, Spain, May 2005.

351

International Interconnect Technology Conference, Burlingame, California, June 1998.

352

Proc. 9th Intl. Workshop an THERMal INvestigations of ICs and Systems, Aix-en-Provence, France, Sept. 2003. TIMA,
0-7803-7999-3.

353

E. Zschech, K. Maex, P.S. Ho, H. Kawasaki, and T. Nakamura, Eds.,
Stress-Induced Phenomena in Metallization. AIP Conference Proceedings, 2006.

354

Proc. of the 201th Meeting of The Electrochemical Society: Fifth Intl. Symposium On Chemical Mechanical Polishing, Philadelphia, PA, May 2002.

355

Proc. IASTED Intl. Conf. on Applied Modelling and Simulation, Honolulu, Hawaii, USA, Aug. 1998.