Chapter 4
Next Generation FETs Based on 2D Materials

A significant portion of this work will be devoted to the characterization of the reliability of next-generation FETs based on 2D materials, which are currently being intensively studied. Therefore, in the course of this chapter a brief review of 2D materials from graphene and beyond, which are suitable for applications in modern micro- and nanoelectronic devices, will be provided. Also, an overview of research on transistors with graphene and MoS₂ and their properties will be provided. This information will be useful for understanding the results described in the following chapters.

4.1 Overview of 2D Materials: Graphene, MoS₂ and Beyond

The term “2D materials” combines a wide range of crystalline materials with exciting electro-physical, magnetic and optical properties [20, 71]. Although the first studies of 2D materials are known since the late sixties [123, 185], an intensive research in this direction has started only in the last decade [195, 22, 99, 182]. The main reason for this is the understanding that sooner or later conventional scaling of Si devices, as known from Moore’s Law, will come to an end. This creates a demand to go beyond conventional CMOS technology by using principally different material systems. In particular, the primary advantage of 2D materials, i.e. the creation of atomically thin channel layers below 1nm and the stacking of them in versatile ways, has introduced an extremely rich spectrum of new possibilities in modern science and technology [22].

Based on literature reports [133, 21, 3, 130, 12, 18, 22, 32, 35, 49, 126, 190, 135, 87, 138, 51, 88, 91, 99, 182, 20], the major fraction of 2D materials can be classified into three main subclasses. The first and the largest of them is 2D chalcogenides, which include such semiconducting transition metal dichalcogenides (TMDs) as MoS₂, WS₂, WSe₂, MoSe₂ [3, 35, 49, 51, 91], metallic dichalcogenides like NbSe₂, TaS₂, NiSe₂, NbS₂ [22, 35, 49] and layered semiconductors (GaSe, GaTe, InSe, etc)[49]. The second subclass combines graphene-like materials, including graphene itself[133, 12, 18, 88, 28], its derivatives (e.g. wide bandgap fluorographene[130]), boron carbon nitride (BCN)[87], hexagonal boron nitride (hBN) [32, 126, 182] and graphene oxide [138]. Finally, 2D oxides like, e.g. metallic oxides (MoO₃, WO₃, TiO₂, etc)[135], Perovskite-type oxides (LaNb₂O₇, Ca₂Ta₂TiO₁₀, etc) [135] and hydroxides (Ni(OH)₂, Eu(OH)₂, etc.) [49] form the third class of 2D materials. Also, research attention has now shifted to principally new 2D materials, like phosphorene [115, 145], silicene [179, 38, 85] and germanene [31].

Since in the course of this work we are dealing with next-generation 2D FETs, those 2D materials suitable for application either as a device channel or gate dielectric are of the largest interest. Therefore, the following detailed description will be mainly devoted to such channel materials as graphene and semiconducting TMDs (mainly MoS₂). Although devices based on phosphorene, silicene and germanene will not be studied in this work, some brief information about these materials will be provided. This should be useful for understanding of the future development of 2D transistor technologies in general. In addition, the properties of hBN, which is now considered as a next-generation 2D gate insulator [126], will be briefly discussed.

4.1.1 Graphene: Structure and Main Properties

Graphene was already theoretically predicted in 1969 [123], when a detailed analysis of previously published low-energy electron diffraction (LEED) data from single-crystal metallic substrates exposed to hydrocarbons [72, 128] was performed. However, the field effect in highly-stable graphene layers was first reported only in 2004 [133]. Since then graphene has attracted considerable attention due to its unique physical and electrical properties, such as an extremely high room-temperature carrier mobility [50, 133] and high saturation velocity [36].

Graphene is a 2D crystalline allotrope of carbon with a hexagonal lattice structure consisting of a single layer of carbon atoms (Figure 4.1). Each of these atoms has three σ-bonds with its closest neighbours and one π-bond with an orientation outside the 2D plane of graphene. The former is associated with a combination of s, p_x and p_y orbitals of carbon atoms, while the latter is made by the last p_z electron. Thus, sp² bonding of carbon atoms, together with their tight packing in hexagonal lattice (distance between two closest neighbours is just a₀=1.42Å), leads to an extremely high stability of graphene layers. On the other hand side, hybridization of π-bonds leads to the formation of π- and π^*- bands. These bands make free transport of carriers possible, leading to most of the fascinating electrical properties of graphene [28].

Figure 4.1: 2D hexagonal structure of graphene formed by carbon atoms (reproduced using QuantumWise Virtual Nanolab). The lattice constant a = a₀ = 2.46Å.

The band structure of graphene can be calculated from the solution of the Schroedinger equation using the tight binding approach [180], which takes into account only the interactions between the closest neighbours. The resulting energy dispersion expressed using the x and y components of the wave vector k reads

(4.1)

where γ = 3eV is a tight binding parameter and a = a₀ = 2.46Å is the lattice constant. This energy dispersion is shown in Figure 4.2. Clearly, at the edges of the Brillouin zone the conduction and valence bands touch each other, which means that the bandgap of graphene is equal to zero. The corresponding energy is conventionally known as the Dirac point, or charge neutrality point[132]. When an intrinsic graphene is in equilibrium, its Fermi level is alligned at the Dirac point, which corresponds to the middle of the bandgap in conventional semiconductors.

Near the Dirac point, equation 4.1 can be approximated as

(4.2)

where ℏ is the Planck constant, v_f = 10⁸cm/s is the Fermi velocity in graphene [132] and k is the absolute value of the wave vector having the components k_x and k_y. This linear dispersion law is similar to that of photons. Therefore, electrons and holes in the proximity of the graphene Dirac point have zero effective mass, while their velocity is independent of the energy. This is in contrast to parabolic dispersion laws containing an effective mass, which are typical for most other systems.

While in a conventional 2D electron gas with a parabolic dispersion law the density of states is independent of energy, in the case of graphene the linear dispersion law leads to a linear dependence of the density of states versus energy [6]

(4.3)

where g_s = g_v = 2 are spin and valley degeneration degrees, respectively. Therefore, at zero energy no carriers are present.¹ At the same time, electrons and holes in graphene have to be considered as fermions with zero effective mass, which leads to the following equations for their concentrations n and p, respectively [196]

(4.4)

(4.5)

Also, since the momentum k in equation 4.2 is related to the concentration of electrons as k = , the Fermi level E _F and carrier concentrations can be modulated by applying an external electric field. This is typically done by varying the gate voltage of graphene FETs.

The unique 2D structure of graphene results in this material having a number of outstanding properties. The main and most attractive of them is an extremely high carrier mobility at room temperature, which can reach 100000cm²/Vs [17]. Another important property of graphene is a considerable saturation velocity. According to [36], it can exceed 3×10⁷cm/s at low carrier concentrations. Furthermore, the saturation velocity of graphene remains larger than those of Si within the whole range of carrier concentrations at which FETs typically operate (1×10¹²–1×10¹³cm^-2). This is especially valuable for application of graphene in short channel devices. In addition, graphene has an Ohmic contact resistance with metallic electrodes, while its magnitude can be just 50Ω×μm [189]. This allows to achieve high carrier mobilities in graphene devices. Finally, graphene has a high mechanical stability [102], optical transparency [129] and thermal conductivity [157]. These properties are also essential for application of this material in next-generation electronics devices.

Currently, graphene layers can be successfully synthesized using a large number of different methods [39]. However, the zero bandgap of graphene significantly limits the potential of its practical applications. In particular, this disadvantage makes fabrication of high on/off ratio graphene-based transistors impossible, though such devices are required for application in digital circuits. Although several attempts have been undertaken to artificially open the bandgap in graphene (e.g. by using dopants [144] or create nanoribbons [73, 111]), this typically leads to a considerable decrease in mobility, the most fascinating property of graphene. Therefore, in addition to intensive graphene research, alternative 2D materials are being sought.

4.1.2 MoS₂ as a Further Step Beyond Graphene

Molybdenum disulfide (MoS₂) is one of the transition metal dichalcogenides now considered a promising candidate for future device applications. This material has a layered structure consisting of S-Mo-S monolayers, which are formed by hexagonally arranged Mo and S atoms. In MoS₂ crystals these layers are stacked together by weak van-der-Waals interactions, while the thickness of a single layer is 6.5Å [141]. The geometry of MoS₂ layers reproduced using QuantumWise Virtual Nanolab is shown in Figure 4.3.

A long time ago it was found that bulk MoS₂ crystals exhibit semiconducting properties, while having an indirect bandgap of 1.2eV [92]. Owing to recent technological progress [134, 174], single-layer MoS₂ has become an interesting semiconducting counterpart of graphene, which has a similar 2D hexagonal structure but no bandgap. The first-principles calculations of the electronic structure of single-layer MoS₂ was performed in [91], where the authors employed the Kohn-Sham density functional theory [77]. These simulations reapproved [120] that single-layer MoS₂ is a direct bandgap semiconductor with a sizable bandgap of 1.79eV. This allows the main limitation of graphene to be overcome, making MoS₂ suitable for application in logic devices. At the same time, a single-layer MoS₂ has a parabolic dispersion relation in the proximity of the valence band maximum and conduction band minimum (K-point), while having considerable effective masses (m_e^* = 0.54m ₀ and m_h^* = 0.44m ₀ for electrons and holes [91], respectively).

Another important property of thin MoS₂ layers is a high intensity of the photoluminescence signal [120], which originates from the direct optical transitions at the K point [91]. Therefore, this material is now being successfully applied in optical detectors [118] and electroluminescence devices [163].

A significant disadvantage of MoS₂ compared to graphene is a considerably lower mobility. The room temperature values for bulk MoS₂ crystals are 200–500cm²/Vs [44], which is limited by phonon scattering. However, for single-layer MoS ₂ on SiO₂ substrates, these values are typically reduced to 0.1–10cm²/Vs [104, 140]. Nevertheless, further development of MoS ₂ device technologies has significant potential to go far beyond these small values. The two main directions in this context are the use of non-SiO₂ substrates, such as hBN [104], and the engineering of metallic contacts with low resistance (e.g. molybdenum [95]). The most realistic goal would be to outperform graphene with an artificially introduced bandgap.²

As for the fabrication of single-layer MoS₂, currently the most wide spread techniques are mechanical exfoliation [134] and chemical vapour deposition (CVD) [174]. However, mechanical exfoliation allows for the obtainment of high quality crystals of single-layer MoS₂ with small grain sizes, typically below 10μm. Conversely, the grain sizes of CVD MoS₂ crystals can be as large as 120μm [174]. Therefore, the second technique is more suitable for mass production.

Although MoS₂ has attracted a considerable amount of attention, this is only one material from a wide range of 2D TMDs. At the same time, it has been shown that many other TMDs with similar properties (e.g. TiS₂, TaS₂, WS₂, MoSe₂, WSe₂) outperform the bandgapless graphene in many ways, especially in FETs for digital applications [122]. Thus, intensification of research in this direction is expected in the near future.

4.1.3 Phosphorene, Silicene and Germanene: New Era in Semiconductor Science

Phosphorene is an almost unexplored 2D counterpart of bulk black phosphorous, which was only reported in 2014 [115, 145]. First calculations performed in [115] show that this material has a direct bandgap, which depends on the number of layers and also the in-layer strain. Phosphorene is now considered a promising material capable of outperforming graphene in digital device applications. At the same time, its comparably high hole mobility (286cm²/Vs) [115] makes phosphorene a promising candidate as a channel material in p-FETs. This allows limitations of MoS₂, which typically acts as an n-channel material [142], to be overcome. Finally, the high flexibility of phosphorene allows its mechanical exfoliation [183] to be performed, which significantly simplifies fabrication of device prototypes.

Further research for 2D materials capable of overcoming the limitations of graphene has led the research community to the 2D counterparts of Silicon (silicene) [179, 38, 85] and Germanium (germanene) [31]. Together with phosphorene, these, and perhaps other 2D counterparts of well-known semiconductors, may open a new era in sub-Silicon semiconductor device technologies in the near future.

4.1.4 Hexagonal Boron Nitride as a Next-Generation 2D Insulator

Hexagonal boron nitride (hBN) [136, 32, 182] is one of the most widely used phases of boron nitride, and is also known as “white graphene”. As shown in Figure 4.4, the structure of the hBN layer presents a set of hexagonal honeycombs similar to that of graphene. However, alternating atoms of boron and nitrogen are linked by highly polar covalent B-N bonds, in contrast to non-polar C-C bonds in a graphene sheet. At the same time, different layers in multi-layer structures are stacked by van-der-Waals interactions.

Although hBN belongs to the graphene family of 2D materials, its electrical properties are dramatically different. The most important in the context of this work is that hBN has a wide direct bandgap of around 5.9eV[136]. Together with a crystal structure, that is similar to that of most widely used 2D semiconductors, and the absence of dangling bonds, this makes hBN a promising candidate for the use as a gate insulator in next-generation 2D FET technologies [32, 126, 104].

Initially, hBN insulating layers attracted a considerable amount of attention in attempts to improve the performance of graphene FETs (GFETs) [32, 126]. In particular, in [32] it was shown that the mobility achieved in GFETs made on hBN substrates is considerably larger compared to similar devices on SiO₂. However, in the meantime hBN has been successfully applied as a gate insulator in MoS₂ FETs, also leading to a significant improvement in mobility [104].

While being extremely stable, hBN monolayers can be produced using the same methods as many other 2D materials. Namely, either mechanically or via liquid phase exfoliation as well as CVD can be used [182]. This makes simple assembly of hBN into technological processes used for manufacturing of next-generation 2D devices possible. For example, creation of hBN/MoS₂/hBN stacks is possible [103].

4.2 Properties of Graphene FETs

The discovery of an electric field effect in graphene in 2004 [133] allowed this material to be considered as a new building block for modern FETs. Therefore, already in 2007 the first field-effect device with a graphene channel was reported [108]. Since then, many successful attempts at fabricating GFETs [112, 98, 127, 126, 82, 32, 74, 125, 40, 117] and related electronic devices, such as graphene barristors [192] and graphene hot electron transistors [176], have been undertaken.

4.2.1 Different Realizations of GFETs

Depending on the device configuration, GFETs known from the literature are either back-gated [126, 82, 32, 74, 117] or top-gated [108, 112, 127, 98, 40], see Figure 4.5. In back-gated GFETs, the graphene channel is situated on top of the Si/SiO₂ substrate (Figure 4.5(left)). Therefore, the SiO₂ layer, which is obtained by thermal oxidation of Si [112, 82, 74, 117], serves as a gate insulator, while Si is employed as a gate electrode. The graphene channel is typically made by mechanical exfoliation on top of SiO₂ [32] or by CVD [74], while the latter method leads to significant uniformity of the film [74]. The source/drain electrodes (e.g. TiAu) can be created by using electron-beam lithography followed by a lift-off process [117]. Also, for convenience during measurements, a metallic electrode connected to a Si substrate can be added. However, back-gated devices are quite complicated for integration into circuits, and their performance is limited by large parasitic capacitances and the detrimental impact of the environment on the non-covered graphene layer [117]. Therefore, they are mostly suitable for use as test benches when investigating the carrier transport processes in graphene. Thus, devices required for circuit applications have to be equipped with a top gate.

In top-gated devices, the graphene channel is sandwiched between a back gate insulator (SiO₂) and a top gate insulator (typically high-k) with the top gate electrode placed on top (Figure 4.5(right)). Obviously, realization of top-gated GFETs requires additional technological steps compared to their back-gated counterparts. First, after transferring graphene on top of SiO₂, the high-k top gate oxide (e.g. HfO₂ or Al₂O₃) is grown by atomic layer deposition (ALD) [112, 40]. Second, additional lithography steps are necessary to create the top gate electrode and make the device electrically accessible [40]. Also, since top-gated devices typically have two gate contacts, they can be referred to as “double-gated” (in particular, in this work).

The schematic plots in Figure 4.5 illustrate those realizations of GFETs which in the meantimes are the most commonly used. However, in the literature one can find GFETs with more exotic configurations. For example, the authors of [32, 126] report on back-gated devices with hBN gate insulators. The top-gated GFETs described in [127] are made on the SiC substrate with the graphene channel epitaxially grown on top of it, with no back gate SiO₂ layer. Finally, in [40] Si₃N₄ is used as a back gate insulator. Obviously, all these realizations introduce new technological steps to standard GFETs fabrication techniques, while targeting an improvement of device performance.

4.2.2 Operation and Reliability

As has been mentioned, the position of Fermi level in graphene can be modulated by an external electric field. By varying the voltages applied at the gates (i.e. potential difference between the channel and gates) one can change the carrier concentrations and even the conductivity type of the GFET channel. The latter is due to the zero bandgap of graphene, which leads to the ambipolar behaviour of GFETs. The change of the GFET conductivity type takes place when the Fermi level is aligned at the Dirac point (E_cv). Obviously, this is realized when the potential difference between the channel and gates is equal to work fuction difference. In the general case of double-gated GFETs, this is equivalent to a zero effective gate voltage [196], which reads

(4.6)

where C_tg and C_bg, and V _tg and V _bg are the top and back gate capacitances and voltages, respectively. The quantities V _NP^tg and V _NP^bg have the physical meanings of charged neutrality biases (Dirac points) of uncorrelated devices with only a top gate and only a back gate. They are given as

(4.7)

(4.8)

with W_tg, W_bg and χ_gr being the work functions of the top gate, back gate and graphene. N_T^tg and N _T^bg are the concentrations of charged traps in the top gate and back gate oxides, respectively. Therefore, the top gate Dirac point voltage at fixed V _bg reads

(4.9)

Similarly, if the device is tested at constant V _tg while sweeping V _bg, the back gate Dirac point voltage³ is

(4.10)

Therefore, one of the main parameters which determines the position of the Dirac point is the density of charges in the corresponding oxide. This quantity is also responsible for the dielectric reliability and typically changes during stress, which make this correlation extremely important for the interpretation of our experimental results below. Also, it is worth noting that if the back gate oxide is much thicker than its top gate counterpart, V _D^tg ≈V _NP^tg. Since variations of work functions and gate capacitances during device operation (stress) are negligible, for devices with a thick back gate, N_T^tg is the only dynamic parameter responsible for the Dirac point position. Also, equations 4.9– 4.10 show that in double-gated GFETs the Dirac point can be modulated by the voltage applied at the opposite gate electrode.

One should note that in general the top and back gate capacitances used above may differ from geometric capacitances. This originates from the 2D nature of graphene, which leads to a limited density of states D(E) (equation 4.3). Thus, it is necessary to account for the quantum capacitance C_q = q²D(E) [42]. This quantum capacitance is connected in series with the geometric capacitance C_g = ε_g∕d_g, with the gate dielectric constant ε_g and oxide thickness d_g. However, since the typical oxide thicknesses used in GFETs are quite large, the contribution of C_q in most cases is not very significant. Nevertheless, it always worth estimating the impact of the quantum capacitance.

The typical transfer (I_d-V _g) characteristic of a GFET is shown in Figure 4.6. It has a parabolic-like shape with a minimum of the drain current at the Dirac point. Hence, if the applied gate bias is below V _D, the Fermi level lies in the valence band of graphene. This leads to a hole conductivity type of the channel. In contrast, at V _g above the Dirac point the Fermi level is inside the conduction band of graphene, leading to electron transport. In the context of device reliability, this behaviour means that NBTI corresponding to V _g - V _D<0 is associated with hole trapping, while PBTI at V _g - V _D>0 leads to electron trapping. Therefore, in the former case the created defects are positively charged, while in the latter case negatively charged defects are introduced.

However, the symmetric transfer characteristic sketched in Figure 4.6 corresponds to an ideal GFET. In reality, the difference between the electron and hole mobility and the impact of the contact resistance may lead to a considerable asymmetry between the behaviour left and right from the Dirac point [191]. In addition to limitations introduced by device fabrication, this significantly complicates simulations of GFETs. Nevertheless, several compact models allowing for the reproduction of the main characteristics of GFETs have been reported [98, 164, 4, 165, 196]. The most interesting in the context of this work is the paper by Ancona [4], in which an attempt to adjust the drift-diffusion model to the case of GFETs has been undertaken. This idea will be further developed in the course of this work, which will help in the interpretation of our experimental results.

Another interesting property following from the ambipolar nature of graphene is that, contrary to Si FETs, there is no pinch-off behaviour. Instead, if the drain bias V _d is large enough, the device channel can be of an ambipolar nature [125]. Namely, while a considerable part of the channel is n-type, at high V _d the conductivity type of some near-drain regions can change to p-type. As will be shown (Figure 6.2), this typically leads to some signs of the second linear region (“kinks”) on the output (I_d-V _d) characteristics.

We assume that, similarly to Si MOSFETs, the main reliability issues in GFETs should be NBTI, PBTI and HCD. Obviously, recent successes in fabrication of GFETs have created a demand for a detailed study of these phenomena. However, only a few attempts to describe BTI in GFETs have so far been reported [82, 113, 116, 117]. While basic concepts of the BTI origin in GFETs have been understood, there are no systematic studies of this issue. At the same time, nothing at all has been reported about HCD in GFETs. Thus, in the context of this work, a lack of understanding of the reliability of GFETs opens wide a new area of investigation.

4.3 MoS₂ FETs: an Important Step Beyond GFETs

Practical realization of high-performance devices based on 2D materials is a very attractive idea. However, limitations of graphene due to the zero bandgap do not allow for the creation of GFETs with a high on/off current ratio. Therefore, implementation of MoS₂ as a new building block for next-generation FETs has become a must. The first transistor with MoS₂ was reported in 2011 [141]. While having a single-layer MoS₂ channel, this device could exhibit an on/off ratio as high as 10⁸ and a mobility of 200cm²/Vs.⁴ In the same year an attempt to estimate the potential limits of the performance of MoS₂ FETs was undertaken [195]. By performing self-consistent simulations of quantum transport through a MoS₂ layer, the authors of [195] have shown that MoS₂ FETs can reach a transconductance as large as 4.4mS/μm and an on/off ratio of >10¹⁰, together with an excellent short-channel behaviour. These advances resulted in a more intensive investigation of MoS₂ properties. Thus, numerous groups succeeded at fabricating MoS₂ FETs in the next few years [30, 140, 101, 52, 104, 43, 110, 193, 95, 24, 100].

The absolute majority of MoS₂ FETs known from the literature are of a back-gated configuration [30, 140, 101, 52, 104, 43, 110, 193, 95, 24, 100]. Similarly to GFETs, they are typically fabricated on Si/SiO₂ substrates with thermally grown SiO₂, which serves as a gate insulator. However, in some devices Al₂O₃ grown by ALD right on the Si substrate is employed [24, 95]. Also, the use of transferred hBN as a back gate insulator is possible, while leading to a significant mobility increase [104]. The MoS₂ channel is typically fabricated by mechanical exfoliation from bulk crystals on top of a back gate insulator (e.g. [43, 100]), while being covered by an Al₂O₃ passivation layer in some cases [43]. The source-drain contacts are made by e-beam evaporation and patterned using ultra-violet photolithography, while the most widely used material is TiAu (e.g. [101, 104, 100]). But, contrary to graphene, MoS₂ forms a Schottky contact at the interface with metals. Thus, in some cases a large Schottky barrier may lead to considerable contact resistances, while reducing the overall device performance. Also, in [30] it was claimed that the interface between MoS₂ and the metal is strongly impacted by Fermi level pinning close to the conduction band of MoS₂. Therefore, the authors of [30] suggest using metals with lower work functions as source and drain contacts for MoS₂ FETs. In particular, devices with Sc contacts show a significantly reduced contact resistance, while exhibiting a transconductance of 4.7μS/μm. Another work [95] reports that the use of Mo contacts also leads to a lower Schottky barrier with MoS₂, which significantly improves transistor performance.

The first MoS₂ FET reported in [141] had a top-gated configuration and employed ALD grown HfO₂ as a top gate insulator. However, direct deposition of a top gate dielectric onto a MoS₂ channel still presents a technological issue. This is because direct ALD of HfO₂ on MoS₂ is not uniform, and no covalent bonding is formed between the two materials [124]. This significantly limits the possibility of integration of MoS₂ FETs in top-gated configuration. Nevertheless, estimation of device performance limits made in [195] have been done for the top-gated geometry which is similar to [141]. Moreover, simulations made by the authors of [23] have shown that the output characteristics of top-gated MoS₂ FETs can exhibit negative differential resistance. Together with a better compatibility of top-gated devices with integrated circuit technology, this makes practical realization of high-performance top-gated MoS₂ FETs the next technological task. One of the first steps in this direction was made in [197], where the use of an ultra-thin (1nm) metal oxide (e.g. Y₂O₃) as a buffer layer between MoS₂ and HfO₂ was suggested. This resulted in a MoS₂/HfO₂ interface with smaller defect density, while leading to excellent device performance (e.g. a mobility of 63.7cm²/Vs and an on/off ratio exceeding 10⁸). However, according to a literature review conducted for the purposes of this thesis, the attempts to fabricate the top-gated MoS₂ FETs are still lacking, leaving more detailed studies of top-gated MoS₂ FETs for the near future.

Another important advantage of MoS₂ FETs is that they have a superior immunity to short channel effects [114]. In particular, a high saturation velocity (2.8×10⁶cm/s) makes MoS ₂ channels highly suitable for nanoscale applications [43]. However, MoS₂ devices have been reported to exhibit n-type behaviour, while their transfer characteristics have a shape similar to Si n-MOSFETs [141, 46]. Since for low-power circuits the use of p-FETs is more favourable, other 2D TMDs are now being studied in this context. For example, in [41] WSe₂ p-FETs with reasonable performance are reported. The authors of [29] claim that the use of different electrodes (Ni as a source and Pd as a drain) leads to ambipolar behaviour of WSe₂ FETs.

At the current stage of research the main reliability issue of MoS₂ FETs is associated with the hysteresis appearing on the transfer characteristics due to charging/discharging of fast oxide traps. As shown in [101, 140, 110, 104, 24], the hysteresis can be considerable, especially when measuring in the ambient [101]. However, the use of gate insulators other than SiO₂, namely Al₂O₃ [24] and especially hBN [104], significantly improves the hysteresis stability of MoS₂ FETs.

Other degradation issues which have already been observed for MoS₂ FETs are NBTI [26, 193] and PBTI [26, 139]. Similarly to GFETs, both issues can be observed on the same device, leading to extremely large threshold voltage shifts [26]. The presence of HCD in MoS₂ FETs was declared in [139], although without detailed interpretation. However, reliability studies of MoS₂ FETs are still lacking compared to a great number of papers reporting various device realizations. Also, such studies do not report analysis of BTI recovery, and have been conducted on devices with SiO₂ which lack perfect performance. Therefore, a detailed reliability study on more advanced MoS₂ FETs, in particular with hBN insulator, is a crucial task of this work.