Limitations of graphene associated with the lack of a bandgap do not allow for the creation of GFETs with a high on/off ratio, thus making integration of these devices into digital circuits impossible. Therefore, alternative 2D materials with considerable bandgaps are currently being sought. One of these materials is MoS2, which is already being successfully applied as a 2D channel in next-generation FETs. However, similarly to the case of GFETs, the level of technology is still far below Si standards and requires further improvement. Hence, the characterization of reliability of MoS2 FETs, i.e. the subject of this chapter, is essential. Moreover, the band structure of MoS2 is more similar to conventional semiconductors rather than graphene. This allows comparably simple implementation of this material into professional simulation software, such as Minimos-NT. Some of these simulation results are discussed at the end of this chapter.
Since the first practical realization of MoS2 FETs in 2011 [141], a number of other attempts at fabricating related devices with either SiO2 [141, 30, 140, 101, 43, 52, 139, 26, 110, 193, 100], Al2O3 [95, 24] or hBN [104] as a gate insulator have been undertaken. Although one could expect each of these attempts to be accompanied by at least some reliability analysis, papers which address the question of MoS2 FETs reliability are still lacking [101, 140, 110, 104, 139, 26, 193, 24]. Moreover, even these few studies are mostly restricted to the observation of a hysteresis in the gate transfer characteristics for different measurement conditions [101, 140, 104, 24, 110], while typically reporting extremely poor hysteresis stability of the analyzed devices. At the same time, attempts to analyze BTI in MoS2 FETs are rare [26, 139, 193]. All are limited to MoS2/SiO2 FETs, while reporting large enough threshold voltage shifts and not providing any detailed analysis of BTI degradation/recovery dynamics. Also, no analysis of BTI characteristics have been reported for MoS2 FETs with hBN gate insulators.
In the course of this chapter we perform a detailed study of both the hysteresis and BTI in single-layer MoS2 FETs with SiO2, hBN/SiO2 and hBN insulators, and capture the correlation between these phenomena. As shown below, the devices analyzed within this work significantly outperform their previously reported counterparts with respect to both hysteresis and BTI stability. Also, contrary to all previous BTI studies of MoS2 FETs, we attempt to capture the observed degradation/recovery dynamics using the models previously developed for Si technologies. While employing the universal relaxation relation as the simplest starting approach, we also provide results simulated using the four-state NMP model, which was adjusted to the case of MoS2 FET. The latter approach allows us to perform a more detailed analysis of experimentally observed reliability features.
We examine single-layer MoS2 FETs with SiO2 and hBN as a gate insulator fabricated by our collaborators at Prof. Mueller’s group [47]. The channel length of these devices is around 1μm, while the width for different FETs can vary between 4μm and 8μm. In our MoS2/SiO2 devices (Figure 7.1(left)) a MoS2 channel is situated on top of a 90nm thick SiO2 layer. In the second transistors, MoS2 is sandwiched between two 90nm thick hBN layers (Figure 7.1(right)). In order to allow for a more detailed analysis of hBN vs. SiO2, we added an additional Ti/Au gate between the hBN and the SiO2 layer. Thus, we can operate these devices either with a hBN gate insulator when contacting the Ti/Au plate or with a hBN/SiO2 stack through the highly doped Si substrate.
The MoS2/SiO2 devices were fabricated on double side polished and thermally oxidized Si substrates with a resistivity of 1 – 5Ω×cm and SiO2 thickness of 90nm. MoS2 flakes were mechanically exfoliated from a natural bulk crystal on top of a SiO2 layer using the method [48]. After, the flakes with the optimal quality were selected using an optical microscope and their final thickness was determined by Raman spectroscopy. This was done in order to identify those with single-layer MoS2 thickness (i.e. around 6.5). Then Ti/Au electrodes were created by electron beam lithography and metal evaporation techniques (e.g. [101]).
In the case of MoS2/hBN devices, a 22nm thick Ti/Au back gate pad was evaporated on top of a 90nm thick SiO2 layer. Next, the hBN/MoS2/hBN stack produced using the stacking method [103] was placed on top of the Ti/Au pad. The essential ingredients of this stack are mechanically exfoliated single-layer MoS2 flakes and two 90nm thick hBN layers, also obtained from bulk hBN crystals1 using mechanical exfoliation. While single-layer MoS2 flakes were identified using Raman spectroscopy, the thickness and quality of hBN flakes were controlled using atomic-force microscopy. Also, those hBN flakes which were used as the uppermost layer were pre-structured by electron beam lithography and reactive ion etching in order to create the slots for source and drain contacts. Finally, Ti/Au electrodes were created using electron beam lithography and metal evaporation.
For the primary check of the performance of our devices we measured their gate transfer (Id-V g) and output (Id-V d) characteristics. The results obtained for MoS2/SiO2 and MoS2/hBN FETs are shown in Figure 7.2. Similarly to [101, 104], the gate transfer characteristics of our devices exhibit the behaviour typical for n-FETs with some hysteresis. The latter is associated with charging/discharging of fast traps. Interestingly, for the devices with hBN, the hysteresis is significantly smaller than for their counterparts with SiO2, which is in agreement with [104]. At the same time, the output characteristics of both types of our devices show a quasi-linear behaviour, which is a consequence of the narrow drain voltage intervals [101, 104]. The estimated mobility can reach 1cm2/Vs for MoS 2/SiO2 FETs and 3cm2/Vs for MoS 2/hBN devices. This is larger than for devices with a small number of MoS2 layers and similar channel length [140], while the on/off ratio measured with high current resolution can exceed 105.
Similarly to GFETs, the devices with MoS2 are very sensitive to the detrimental impact of the environment [101]. Therefore, all our measurements were performed in a vacuum (5×10-6–10-5torr), while the temperature was either 25∘C or 85∘C.
The hysteresis was investigated by measuring the Id-V g characteristics using V d=0.1V and different sweep rates S. In order to capture the full frequency range of the fast traps responsible for the hysteresis, S = V step∕tstep was varied between 0.04 and 8000V/s by adjusting the step voltage V step and the sampling time tstep.
The BTI behaviour of MoS2 devices was studied using an experimental technique similar to those previously employed for our GFETs. Namely, subsequent stress/recovery cycles with either increasing stress time ts or gate voltage V g were used for a detailed analysis of BTI degradation/recovery dynamics. By measuring the full Id-V g characteristics of our devices at each recovery stage, we were able to extract the threshold voltage shift ΔV th at a fixed drain current, and express the BTI dynamics in terms of ΔV th(tr) recovery traces.
According to previous literature reports [101, 140, 104], hysteresis stability presents a serious reliability issue for MoS2 FETs at this early stage of research. Hence, we start our reliability analysis with a detailed study of the hysteresis behaviour of our devices with SiO2, hBN/SiO2 and hBN insulators.
An initial check of our MoS2/SiO2 devices shows that the Id-V g characteristics exhibit some hysteresis even after several days in a vacuum at T = 25∘C. While being reproducible at a constant sweep rate, similarly to [101], this hysteresis becomes larger when S is decreased (Figure 7.3a). When the temperature is increased to 85∘C, the drain current increases (Figure 7.3b). At the same time, the hysteresis width ΔV H measured using a very small S significantly decreases. However, when after six days the temperature is changed back to 25∘C, both drain current and hysteresis width show only insignificant trends toward their initial values. Hence, after baking, the device exhibits better performance in terms of both Id and ΔV H. The evolution of the hysteresis for our MoS2/SiO2 devices at different S versus time in the vacuum and temperature is shown in Figure 7.3c. During the first 10 days at T = 25∘C, a large hysteresis was observed for small S, while being reduced versus time in the vacuum. At the same time, no significant hysteresis was present when using fast sweeps. However, when increasing the temperature to 85∘C, ΔV H measured with small S was significantly reduced, while a considerable hysteresis appeared for large S. Back at 25∘C, some increase in hysteresis width measured with small S is pronounced. However, ΔV H did not return to its initial values. This implies that in our MoS2/SiO2 FETs, baking anneals a considerable fraction of slower traps, while also introducing some faster traps. Most likely, slower traps are associated with water molecules [101], which can be evaporated from an uncovered MoS2 surface either during a long time in the vacuum or at higher temperatures. Obviously, in the latter case, annealing of these traps is more intensive, leading to a larger decrease in ΔV H.
We proceed with a detailed analysis of the dependence of the hysteresis width versus sweep rate for our MoS2/SiO2 devices. In Figure 7.4 (left) the dependences of ΔV H versus tstep and V step for different voltage sweep intervals V gmin…V gmax and temperatures are shown. Clearly, in all cases ΔV H increases for larger tstep and smaller V step, i.e. smaller S=V step/tstep. By introducing the measurement frequency f=1/(Ntstep) with the number of points N=2((V gmax-V gmin)/V step+1), we demonstrate in Figure 7.4 (right) that the obtained experimental points form a universal frequency dependence of ΔV H. This behaviour depends strongly on T at low frequencies, confirming that slower traps disappear during baking. For higher frequencies, the dependence becomes more pronounced during and after baking, suggesting that defects with smaller capture times become active. Interestingly, the same trends are observed independently of the sweep range, although ΔV H becomes smaller for narrower sweep ranges (cf. [110]). Thus, in our MoS2/SiO2 FETs the temperature treatment reduces the amount of slower traps and activates faster traps.
In Figure 7.5 we show the transfer characteristics measured at different S and temperatures, and ΔV H(f) dependences for MoS2/hBN/SiO2 device. Similarly to MoS2/SiO2 devices, ΔV H measured using a small S is reduced at higher temperatures, while the fast sweep hysteresis becomes significantly larger. However, the hysteresis is pronounced up to larger S, which suggests the existence of a larger contribution of faster traps compared to MoS2/SiO2 devices. The resulting frequency dependence contains a maximum of ΔV H, which shifts towards higher frequency at T = 85∘C. As such, the temperature dependence is similar to MoS2/SiO2 FETs. Figure 7.6 shows the related results for MoS2/hBN devices. Contrary to the previous two cases, the hysteresis is not present at very small S and can be observed only when using extremely fast sweeps. The frequency dependence confirms that the hysteresis in hBN devices is dominated by ultra-fast traps, while the contribution of slower traps is negligible. Hence, the maximum of ΔV H is most likely at even higher frequencies outside our measurements range. Also, an increase in ΔV H at T = 85∘C is visible for wider sweep range.
The results obtained for MoS2 FETs with different gate insulators allow for a comparison of our finding (see Figure 7.7). While for MoS2/SiO2 FETs the hysteresis is mostly dominated by slower traps, for hBN/SiO2 stacks an increased contribution of faster traps is observed. Hence, in the latter case the maximum of ΔV H lies within our experimental range. At the same time, in MoS2/hBN devices the hysteresis is purely related to ultra-fast traps. Interestingly, in all three cases the temperature dependence is similar. Namely, the contribution of slower traps is reduced and the contribution of faster traps is increased at higher T, leading to a shift of the ΔV H dependence to higher f. In order to compare the maximum values of ΔV H, we normalize them by the scaling factor Krel=K/KhBN with K=(V gmax-V gmin)/dox. This allows to account for the differences in the sweep ranges and insulator thicknesses used for different devices. As shown in Figure 7.7b, our hBN devices exhibit the best hysteresis stability at T = 25∘C. However, their performance deteriorates at higher temperatures, where they are even outperformed by MoS2/SiO2 FETs. Finally, in Figure 7.7c we compare the maximum hysteresis widths (T = 25∘C) normalized by K obtained within this work with the results from [140, 101, 24]. In all cases the measurements have been performed in vacuum because measurements in the ambient show considerably larger ΔV H [101]. Although the hysteresis strongly depends on the temperature, the sweep rate and the gate bias sweep range, we can conclude that our MoS2/SiO2 and MoS2/hBN FETs exhibit the best hysteresis stability. As for the MoS2/hBN/SiO2 devices, they are outperformed only by MoS2/SiO2 devices reported in [24].
Another degradation mechanism which has been reported for MoS2 FETs [26, 139, 193] is associated with bias-temperature instabilities known from Si technologies. Hence, we proceed with characterization of BTI for our MoS2/SiO2 and MoS2/hBN FETs, which have shown the best hysteresis stability.
First we examine our MoS2/SiO2 FETs by applying subsequent PBTI stresses with stress time ts=10ks and increasing V g. The resulting evolution of the Id-V g characterestics is shown in Figure 7.8(left). Clearly, the degradation is recoverable, while being more pronounced for larger V g. Contrary to GFETs and similarly to Si technologies, the BTI degradation/recovery dynamics can be expressed using the threshold voltage shift ΔV th versus the relaxation time tr traces (Figure 7.8(right)). Their analysis shows that the relative ΔV th remaining after tr=10ks decreases from 85% of the initially measured ΔV th for V g = 5V toward 60% for stronger stresses, i.e. for larger V g the degradation is stronger and more recoverable. This is similar to Si technologies.
We proceed with an analysis of the degradation/recovery dynamics in MoS2/SiO2 FETs at different temperatures. Figure 7.9 shows the results obtained using subsequent PBTI stress/recovery cycles with increasing ts. In order to compare the BTI degradation/recovery dynamics with Si technologies, we use the universal relaxation model [61, 64]. All recovery traces for our MoS2/SiO2 devices can be reasonably fitted (Figure 7.9b), since the normalized recovery is universal (Figure 7.9c). Just like in Si technologies, stronger degradation and faster recovery are observed at higher T, which is due to the thermally activated nature of carrier trapping [57]. However, MoS2 FETs are known to exhibit both PBTI and NBTI on the same device [26, 193]. The related results for NBTI in MoS2/SiO2 FETs are provided in Figure 7.10. While V th is shifted in the opposite direction, the observed shifts are larger than for PBTI. This is likely due to a difference in the energy levels of the involved traps. Nevertheless, the recovery traces can be well fitted by the universal relaxation model, which confirms a similarity of the two phenomena. Moreover, the temperature dependence of NBTI degradation is similar to PBTI. Namely, stronger shifts and faster recovery are observed at T = 85∘C.
Next we repeat similar measurements for our MoS2/hBN FETs. The results for PBTI and NBTI are shown in Figure 7.11. While these devices exhibit a negligible degradation at T = 25∘C, at T = 85∘C, both PBTI and NBTI shifts become more pronounced and agree with the universal model. Interestingly, NBTI in MoS2/hBN devices is stronger than PBTI, which is similar to MoS2/SiO2 FETs. Also, use of the universal relaxation model allows us to extrapolate initial shifts ΔV th(tr=0) for both MoS2/SiO2 and MoS2/hBN FETs. The results provided in Figure 7.12 show that ΔV th(tr=0) follow a log(ts) dependence at T = 25∘C and exhibit a power law dependence at T = 85∘C.2 This further confirms that, similarly to Si technologies, carrier trapping in our MoS2 FETs is thermally activated [57].
Hence, we have shown that both PBTI and NBTI recovery in our MoS2 FETs can be reasonably described using the universal relaxation model. Moreover, in Figure 7.13(left) it is shown that the parameters B and β which have been used for fitting of the recovery traces of our MoS2 FETs with SiO2 and hBN are very similar to those previously used for Si technologies and GFETs. This indicates a similarity in the physical processes underlying the BTI dynamics. In Figure 7.13(right) we compare the normalized ΔV th measured within this work with the results from [26, 193]. Clearly, our MoS2/SiO2 FETs show better stability with respect to PBTI stress, while the V th shifts caused by NBTI are comparable to previous literature reports. At the same time, hBN devices exhibit superior BTI reliability. This is in agreement with our hysteresis results, showing that the amount of slow traps in MoS2/hBN FETs is small and that the main reliability issue of these devices is associated with ultra-fast traps. It is also worth noting that, contrary to Si technologies, the degradation in these 2D FETs does not have a permanent component, likely due to the absence of dangling bonds at the interface.
The results above show that the BTI dynamics in our MoS2 FETs are very similar to those in Si technologies. Hence, at the next stage we attempted to perform more sophisticated simulations using the four-state NMP model coupled with the DD model. These simulations were done using our deterministic simulator Minimos-NT[83], which was first applied to describe carrier transport and trapping dynamics in the transistors with 2D channels.
In order to demonstrate the proof of concept, we have created a simulation template with the device geometry of our MoS2/SiO2 FET (Figure 7.1(left)) and a number of traps placed into the gate oxide. The real device dimensions and barrier parameters known from the literature (e.g. [150]) were implemented into the simulations. However, since Minimos-NT was originally developed for modeling of traditional Si MOSFETs, adjusting of this advanced simulator to the case of next-generation 2D technologies presents a complicated trick. Hence, in our first attempt, MoS2 is treated as a conventional material with the thickness of several angstroms. Also, the density of states in the MoS2 channel is described using the standard approach for conventional semiconductors rather than the one employed for 2D electron gas.
In Figure 7.14 we show the results simulated for stress and recovery dynamics of both NBTI and PBTI in MoS2/SiO2 FETs at two different temperatures. Despite several approximations having been done, our Minimos-NT simulations can reasonably reproduce the measured recovery traces and all related trends. In particular, an asymmetry between NBTI and PBTI as well as stronger degradation and faster recovery at higher temperatures fully agree with the four-state NMP model. Remarkably, the activation barriers of different transitions and other model parameters were the same for all four considered cases. Moreover, they are very similar to those previously used for modeling of NBTI in Si MOSFETs[152].
However, in the meantime a reasonable fitting of the experimental results is mostly possible for very long PBTI and NBTI stresses (all traces in Figure 7.14 correspond to ts=10ks). Nevertheless, in some particular cases we can properly reproduce the traces measured for different ts using the same set of parameters. An example of the most successful results for NBTI at T = 85∘C is shown in Figure 7.15. Again, the similarity of the model parameters to the case of Si technologies[152] allows us to conclude that the BTI dynamics in our MoS2 FETs are similar to Si technologies. However, in our simulations for MoS2 devices we consider only the recoverable component of BTI, while the permanent component is neglected. This is similar to the case of GFETs, and most likely associated with the absence of dangling bonds.
Although some reasonable results on modeling of BTI in MoS2 FETs have already been obtained, this simulation technique requires further adjustment. Nevertheless, demonstration of the proof of concept for these simulations, which were done for the first time in the course of this work, is extremely valuable.
In the course of this chapter we have demonstrated that our MoS2 FETs with SiO2 and hBN exhibit a smaller hysteresis and better BTI stability than similar devices reported by other groups. Moreover, hBN as a gate insulator reduces the impact of slow traps and improves BTI reliability. While the main reliability issue in MoS2/hBN FETs is associated with ultra-fast traps, we have shown that at higher T the BTI reliability of hBN is reduced due to thermally activated charge trapping. Also, we have demonstrated that the BTI recovery traces measured for all our MoS2 FETs follow the universal relaxation relation previously developed for Si technologies. Finally, we presented a proof of concept for the modeling of BTI characteristics of our MoS2/SiO2 FETs with Minimos-NT. Although this work requires further efforts, some reasonable results were obtained with the four-state NMP model parameters similar to those previously used for Si MOSFETs. Together with the results for GFETs described in the previous chapter, this underlines that the BTI degradation/recovery dynamics in next-generation 2D FETs are similar to their counterparts in Si technologies. However, no proof of the impact of the permanent component of BTI has been found for 2D devices so far, most likely because of the absence of dangling bonds.