The MOS profile can be extracted from the SiO
/Si interface down to
the maximum extent of the depletion region 
. 
is
calculated using (4.7). Initially 3 knots are placed at
0, 
, and .
After an initial extraction, the fit error is analyzed. Since the
capacitance errors are given at a certain gate voltage,
(4.7) is again used to calculate the depletion
depth that corresponds to this voltage.
The interval with the highest error reduction potential (
) is
identified. For the case of constant voltage steps, is defined
as the sum of absolute errors on that interval:
where n is the number of capacitance measurements that correspond to a
depletion edge, as calculated by (4.7), that is contained
in the knot interval in question.
A new knot is inserted in the middle of that interval and the process is
repeated until the information contained in the measurement data is fully
used and the insertion of new points does not provide any significant
improvement.