It is well known that the performance of CMOS based digital circuits depends
on the current driving capabilities of the PMOS and NMOS transistors as well
as the transistor and interconnect circuit capacitances.
Fluctuations in processing conditions caused by manufacturing disturbances
induce variations in these characteristics. In order to ensure proper circuit
operation these variations have to be taken into account by circuit
designers. A characterization of the center and the extremes of the process
region of variations has proven to be an effective method for the technologist
to communicate the process capabilities to the VLSI circuit designers.
In this section, a method to predict the variation in current driving
capabilities, as measured by the saturation currents of the P- and N-channel
MOSFETs (
and 
) is presented. Variation in other device
and interconnect characteristics will not be addressed. It is noted though
that the same methodology can be extended for these or other more general
performance criteria.