4.3.1 Device Structure and Simulation

Simulation of SOI MOSFETs is challenging because the floating body region introduces a poor condition of the equation system [149,151]. Furthermore, the standard energy-transport equations [152,153,154] cannot be directly applied, because they predict unreasonable output characteristics [155]. In this work the instabilities of the equation system have been reduced by using a special iteration scheme (see Section 3.6.7): in a pre-step, the body potential was fixed to an initial value until convergence was reached. In the second step, the body potential was released until a solution was found. Using this approach, the number of required iterations could be reduced dramatically.

**Figure 4.12:** Output characteristic of a typical SOI MOSFET. When impact-ionization is included in the simulation the kink effect becomes clearly visible.
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soikink/KinkId_xcrv_rot, width=11.5cm}\end{center}\vspace{-0.4cm} \end{figure}$

**Figure 4.13:** Substrate current of a body contacted SOI MOSFET for $V_\textrm {GS}=0.8 \textrm {V}$ .
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soikink/KinkIb_xcrv_rot, width=11.5cm}\end{center}\vspace{-0.4cm} \end{figure}$

SOI technology offers many features, such as excellent isolation, latchup-free operation, a high packing density, or less leakage current. The kink effect in the output characteristic is clearly undesired as it introduces distortions in the output signal. This issue is rather crucial for analog applications. As shown before (see Section 4.1.1) the excess carriers can be drained of by a bulk contact. For LDMOSFETs which are fabricated in thick SOI layers this contact is formed using an additional p

-doping in parallel to the n

-doping at the source contact. For devices fabricated on thin SOI layers of several ten nanometer thickness, this approach is not applicable. Thus the body contact which is used to drain off the excess carriers must be implemented in the third dimension. Fig. 4.14 shows the geometry of the simulated device. The SOI layer thickness is $70\,{\mathrm{nm}}$ , the printed gate length is $0.125\,\mu{\mathrm{m}}$ and the device width

for the shown device is $1.0\,\mu{\mathrm{m}}$ .

**Figure 4.14:** The Geometry of the simulated SOI MOSFET structure. The body contact is formed in the third dimension.
$\begin{figure}\vspace{0.4cm} \begin{center} \psfig{file=figures/soikink/soi_geometry, width=14cm}\end{center}\vspace{-0.4cm} \end{figure}$