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4
Spintronic Memristive Stateful Logic Gates
4.1
Overview
4.2
Implication Logic Using DW-TMR Memristors
4.2.1
DW-TMR Memristor
4.2.2
Domain Wall Dynamics
4.2.3
DW-TMR-Based Implication Logic
4.2.4
Simulation Results and Discussion
4.3
Novel Implication Logic Gates Using STT-MTJs
4.3.1
Device Principles
4.3.2
Reliability Modeling and Analysis
4.3.3
Improved Implication Logic Gate
4.4
Reprogrammable Logic Using STT-MTJs
4.5
Comparison of Improved Implication and Reprogrammable
Gates
4.6
Effect of the MTJ Device Parameters on Reliability
4.7
Summary
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