7  Conclusions and Outlook

TiO-based and spintronic memristive devices as well as implication and reprogrammable circuit topologies are potential candidates as the basic (latch/gate) building blocks of the stateful logic systems. TiO-based memristive implication logic gates are studied based on a nonlinear memristor device model which successfully takes into account the dynamic switching behavior and the nonlinearities observed in TiO memristive devices. The gates are optimized to minimize the state drift error accumulations and to ensure correct implication logic behavior for different input patterns. It is shown that the use of refreshing circuitry after a limited number of logic steps (10–20 steps) is unavoidable due to the state drift errors accumulated in sequential logic steps. This is very unfavorable as it needs extra hardware and increases complexity. Furthermore, limited endurance is still a major challenge for metal/oxide/metal technology to be used as universal memory cells or computing devices.

Spintronic memristive devices, especially the tunnel magnetoresistance (TMR)-based devices, show almost unlimited endurance and sufficiently high resistance modulation. In addition, spintronic devices provide a very fine level of control and faster switching compared to the TiO memristive devices which exhibit a very low mobility of dopants in the TiO thin film. It is shown that the implication logic operation can be implemented based on domain wall (DW) TMR memristive devices, with the DW position serving as state variable. This enables stateful logic operations that extends spintronics from non-volatile memory to logic applications, for which the spintronic memristor serves simultaneously as a logic gate and a latch. However, similar to the TiO-implication gate, the DW-TMR-based gate also suffers from the state drift error accumulation.

The spin-transfer torque magnetic tunnel junction (STT-MTJ) is proposed as a very favorable device for stateful implication logic as it inherently eliminates the state drift error accumulation due to its magnetic bistability. Furthermore, it has a great potential, because of its CMOS compatibility, scalability, unlimited endurance, and fast switching speed. A new improved current-controlled gate topology is proposed for STT-MTJ-based implication logic. Reliability modeling and analysis is presented for optimizing and comparing the STT-MTJ-based logic gates. It is demonstrated that the proposed implication gate provides a more energy-efficient and reliable implementation as compared to the conventional (voltage-controlled) implication gate topology. It is also demonstrated that the implication logic framework based on the proposed gate topology significantly improves the reliability of the MTJ-based logic compared to the earlier proposed reprogrammable logic framework which is based on common Boolean logic operations including AND, OR, et cetera.

STT-MRAM-based logic architectures are presented to facilitate the generalization of the MTJ logic gates to large-scale non-volatile logic circuits. The asymmetry issue of the proposed implication logic gate is addressed by exploiting the access transistors of one-transistor/one-MTJ cells not only as on-off switches but also as voltage-controlled resistor. Therefore, the functionality of the STT-MRAM circuit is extended to include stateful logic operations with no extra hardware added. STT-MRAM stateful logic provides non-volatile logic fan-out, exhibits high flexibility with regard to the delocalized computations execution, and eliminates the need for intermediate circuitry. It also enables parallel non-volatile computations and, therefore, it is suited for large-scale logic applications and opens an alternative path towards zero-standby power logic systems, shifting away from the Von Neumann architecture. It is shown that for the intrinsic (N)AND and (N)OR operations, the reprogrammable gate requires slightly less power than the corresponding implication-based implementation. Besides the fact that the MRAM-based implication logic enables a more reliable logic behavior as compared to the reprogrammable gates, it outperforms the reprogrammable gate for more complex logic functions and is thus the implementation of choice for large-scale logic circuits. Through design examples like fundamental arithmetic functions, the advantages of the MRAM-based stateful logic implementation are described and the possible tradeoffs to optimize the execution time, the energy consumption, and the reliability of the MRAM-based stateful logic architectures are also investigated. It is also shown that, at the cost of reduced reliability, a combined reprogrammable-implication logic architecture reduces the total number of the logic steps and thus the energy consumptions.

The MRAM-based stateful logic via the improved implication logic gate is based on STT-MRAM memory technology which has already been commercialized. However, an experimental demonstration of the improved implication logic gate is still missing. Because of the already reported successful fabrication of the reprogrammable gates, on one hand, and improved reliability of the novel implication gate demonstrated in the thesis, on the other hand, we believe that the fabrication of this novel gate is quite feasible. As it is shown in this work, the reliability is an essential prerequisite of the MTJ-based logic circuits. We demonstrated that the reliability increases almost exponentially with the TMR ratio and the thermal stability factor of the MTJ. Due to the strong ongoing efforts towards improving the STT-MRAM technology, these parameters keep increasing which results in higher reliability. It is demonstrated that, independent of the MTJ switching regime, the improved implication logic gate intrinsically provides a more reliable conditional switching behavior as compared to the reprogrammable gate. Nevertheless, future work may involve the investigation of the level of superiority of the implication gate in subnanosecond (precessional) MTJ switching regime. This is of interest to explore limits and to inquire design tradeoffs in very high-speed MTJ logic architectures. At the architecture level, investigating general methods to design Boolean logic functions based on the basic implication logic operations with minimized logic steps is another necessary future research direction.

The novel functional properties of emerging memristive devices have the potential to lead applications beyond non-volatile memory and logic. The last part of the thesis describes novel charge- and flux-based memristive sensing schemes based on the unique property of memristors to record the time integral of the applied current or voltage signals. The proposed method reduces the capacitance, inductance, and power measurements to a straightforward resistance measurement. Spintronic memristive devices are proposed for both charge- and flux-based capacitance and inductance measurement. The effect of the device geometry on the memristive behavior of a spintronic device caused by the dynamic properties of a propagating magnetic domain wall is studied. Particular geometries corresponding to appropriate memristive characteristics are exploited for charge- and flux-based sensing applications. It is shown that in the presence of the non-adiabatic spin-transfer torque, the spintronic memristor exhibits a constant modulation of the memristance (memductance) with respect to the charge (flux) and can be used for capacitance (inductance) measurement. The memristive sensing method is also suited for novel ultra-low leakage capacitive and inductive sensor applications in nano-scale. For example, the capacitance changes due to any movement of the capacitor plates or a change in the dielectric constant (e.g. due to a finger-touch) can be measured or detected in future memristive capacitive sensors.