[1] International Technology Roadmap for Semiconductors (ITRS), Chapter PIDS, 2011. [Online]. Available: http://www.itrs.net/
[2] V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. I. Bourianoff, “Limits to Binary Logic Switch Scaling - a Gedanken Model,” Proc. IEEE, vol. 91, pp. 1934–1939, 2003.
[3] N. S. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan, “Leakage Current: Moore’s Law Meets the Static Power,” Computer, vol. 36, pp. 68–75, 2003.
[4] K. Rupp and S. Selberherr, “The Economic Limit to Moore’s Law,” Proc. IEEE, vol. 98, pp. 351–353, 2010.
[5] J. Gautier, “Beyond CMOS: Quantum Devices,” Microelec. Engin., vol. 39, pp. 263–272, 1997.
[6] J. A. Hutchby, G. I. Bourianoff, V. V. Zhirnov, and J. E. Brewer, “Extending the Road Beyond CMOS,” Circuits and Devices Magazine, IEEE, vol. 18, pp. 28–41, 2002.
[7] G. I. Bourianoff, P. A. Gargini, and D. E. Nikonov, “Research Directions in Beyond CMOS Computing,” Solid-State Electron., vol. 51, pp. 1426–1431, 2007.
[8] R. Huang, H. Wu, J. Kang, D. Xiao, X. Shi, X. An, Y. Tian, R. Wang, L. Zhang, X. Zhang, and Y. Wang, “Challenges of 22nm and Beyond CMOS Technology,” Sci. China F: Inf. Sci., vol. 52, pp. 1491–1533, 2009.
[9] D. Bouvet, L. Forró, A. M. Ionescu, Y. Leblebici, A. Magrez, K. E. Moselund, G. A. Salvatore, N. Setter, and I. Stolitchnov, “Materials and Devices for Nanoelectronic Systems Beyond Ultimately Scaled CMOS,” in Nanosystems Design and Technology. Springer, 2009, pp. 23–44.
[10] A. C. Seabaugh and Q. Zhang, “Low-Voltage Tunnel Transistors for Beyond-CMOS Logic,” Proc. IEEE, vol. 98, pp. 2095–2110, 2010.
[11] B. Dellabetta and M. J. Gilbert, “Performance Characteristics of Strongly Correlated Bilayer Graphene for Post-CMOS Logic Devices,” Proceedings of Silicon Nanoelectron. Workshop, DOI: 10.1109/SNW.2010.5562544, pp. 1–2, 2010.
[12] S. K. Banerjee, L. F. Register, E. Tutuc, D. Basu, S. Kim, D. Reddy, and A. H. MacDonald, “Graphene for CMOS and Beyond CMOS Applications,” Proceedings of the IEEE, vol. 98, pp. 2032–2046, 2010.
[13] K. Bernstein, R. K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and Architecture Outlook for Beyond CMOS Switches,” Proceedings of the IEEE, vol. 98, pp. 2169–2184, 2010.
[14] V. Sverdlov, Strain-Induced Effects in Advanced MOSFETs, S. Selberherr, Ed. Springer-Verlag, Wien - New York, 2011.
[15] D. E. Nikonov and I. A. Young, “Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking,” Proc. IEEE, vol. 101, pp. 2498–2533, 2013.
[16] S. A. Wolf, D. D. Awschalom, R. A. Buhrman, J. M. Daughton, S. V. Molnar, M. L. Roukes, A. Y. Chtchelkanova, and D. M. Treger, “Spintronics: a Spin-Based Electronics Vision for the Future,” Science, vol. 294, pp. 1488–1495, 2001.
[17] D. D. Awschalom, D. Loss, and N. Samarth, Semiconductor Spintronics and Quantum Computation. Springer, 2002.
[18] D. D. Awschalom, M. E. Flatté, and N. Samarth, “Spintronics,” Scientific American, vol. 286, pp. 66–73, 2002.
[19] A. Ney, C. Pampuch, R. Koch, and K. H. Ploog, “Programmable Computing with a Single Magnetoresistive Element,” Nature, vol. 425, pp. 485–487, 2003.
[20] I. Žutić, J. Fabian, and S. D. Sarma, “Spintronics: Fundamentals and Applications,” Rev. Mod. Phys., vol. 76, p. 323, 2004.
[21] M. Fuhrer, “Spintronics: A Path to Spin Logic,” Nat. Phys., vol. 1, pp. 85–86, 2005.
[22] C. Chappert, A. Fert, and F. N. V. Dau, “The Emergence of Spin Electronics in Data Storage,” Nat. Mater., vol. 6, pp. 813–823, 2007.
[23] Y. Huai, “Spin-Transfer Torque MRAM (STT-MRAM): Challenges and Prospects,” AAPPS Bull., vol. 18, pp. 33–40, 2008.
[24] A. Fert, “Nobel Lecture: Origin, Development, and Future of Spintronics,” Rev. Mod. Phys., vol. 80, p. 1517, 2008.
[25] L. Bogani and W. Wernsdorfer, “Molecular Spintronics Using Single-Molecule Magnets,” Nat. Mater., vol. 7, pp. 179–186, 2008.
[26] B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta, “Proposal for an All-Spin Logic Device with Built-in Memory,” Nat. Nanotechnol., vol. 5, pp. 266–270, 2010.
[27] S. Sanvito, “Molecular Spintronics,” Chem. Soc. Rev., vol. 40, pp. 3336–3355, 2011.
[28] R. Jansen, “Silicon Spintronics,” Nat. Mater., vol. 11, pp. 400–408, 2012.
[29] G. H. Fecher, Spintronics: From Materials to Devices. Springer, 2013.
[30] M. N. Baibich, J. M. Broto, A. Fert, F. N. V. Dau, F. Petroff, P. Etienne, G. Creuzet, A. Friederich, and J. Chazelas, “Giant Magnetoresistance of (001)Fe/(001)Cr Magnetic Superlattices,” Phys. Rev. Lett., vol. 61, pp. 2472–2475, 1988.
[31] G. Binash, P. Grünberg, F. Saurenbach, and W. Zinn, “Enhanced Magnetoresistance in Layered Magnetic Structures with Antiferromagnetic Interlayer Exchange,” Phys. Rev. B, vol. 39, pp. 4828–4830, 1989.
[32] H. Fujimori, S. Mitani, and S. Ohnuma, “Tunnel-Type GMR in Metal-Nonmetal Granular Alloy Thin Films,” Mater. Scien. and Engin. B, vol. 31, pp. 219–223, 1995.
[33] S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki, and K. Ando, “Giant Room-Temperature Magnetoresistance in Single-Crystal Fe/MgO/Fe Magnetic Tunnel Junctions,” Nat. Mater., vol. 3, pp. 868–871, 2004.
[34] S. S. P. Parkin, C. Kaiser, A. Panchula, P. M. Rice, B. Hughes, M. Samant, and S.-H. Yang, “Giant Tunnelling Magnetoresistance at Room Temperature with MgO (100) Tunnel Barriers,” Nat. Mater., vol. 3, pp. 862–867, 2004.
[35] B. N. Engel, J. Akerman, B. Butcher, R. W. Dave, M. DeHerrera, M. Durlam, G. Grynkewich, J. Janesky, S. V. Pietambaram, N. D. Rizzo, J. M. Slaughter, K. Smith, J. J. Sun, and S. Tehrani, “A 4-Mb Toggle MRAM Based on a Novel Bit and Switching Method,” IEEE Trans. Magn., vol. 41, pp. 132–136, 2005.
[36] J.-G. J. Zhu and C. Park, “Magnetic Tunnel Junctions,” Materials Today, vol. 9, pp. 36–45, 2006.
[37] S. Ikeda, J. Hayakawa, Y. M. Lee, F. Matsukura, Y. Ohno, T. Hanyu, and H. Ohno, “Magnetic Tunnel Junctions for Spintronic Memories and Beyond,” IEEE Trans. Electron Devices, vol. 54, pp. 991–1002, 2007.
[38] E. Chen, D. Apalkov, Z. Diao, A. Driskill-Smith, D. Druist, D. Lottis, V. Nikitin, X. Tang, S. Watts, S. Wang, S. Wolf, A. Ghosh, J. Lu, S. Poon, M. Stan, W. Butler, S. Gupta, C. Mewes, T. Mewes, and P. Visscher, “Advances and Future Prospects of Spin-Transfer Torque Random Access Memory,” IEEE Trans. Magn., vol. 46, pp. 1873–1878, 2010.
[39] C. Augustine, N. Mojumder, X. Fong, H. Choday, S. P. Park, and K. Roy, “STT-MRAMs for Future Universal Memories: Perspective and Prospective,” Proceedings of the 28 International Conference on Microelectronics (MIEL), pp. 349–355, 2012.
[40] K. L. Wang, J. G. Alzate, and P. K. Amiri, “Low-Power Non-Volatile Spintronic Memory: STT-RAM and Beyond,” J. Phys. D: Appl. Phys., vol. 46, p. 074003, 2013.
[41] T. Miyazaki, T. Yaoi, and S. Ishio, “Large Magnetoresistance Effect in 82Ni-Fe/Al-AlO/Co Magnetic Tunneling Junction,” J. Magn. and Magn. Mater., vol. 98, pp. L7–L9, 1991.
[42] T. S. Plaskett, P. P. Freitas, N. P. Barradas, M. F. D. Silva, and J. C. Soares, “Magnetoresistance and Magnetic Properties of NiFe/Oxide/Co Junctions Prepared by Magnetron Sputtering,” J. Appl. Phys., vol. 76, pp. 6104–6106, 1994.
[43] T. Miyazaki and N. Tezuka, “Giant Magnetic Tunneling Effect in Fe/AlO/Fe Junction,” J. Magn. and Magn. Mater., vol. 139, pp. L231–L234, 1995.
[44] J. C. Slonczewski, “Current-Driven Excitation of Magnetic Multilayers,” J. Magn. and Magn. Mater., vol. 159, pp. L1–L7, 1996.
[45] L. Berger, “Emission of Spin Waves by a Magnetic Multilayer Traversed by a Current,” Phys. Rev. B, Condens. Matter, vol. 54, pp. 9353–9358, 1996.
[46] E. B. Myers, D. C. Ralph, J. A. Katine, R. N. Louie, and R. A. Buhrman, “Current-Induced Switching of Domains in Magnetic Multilayer Devices,” Science, vol. 285, pp. 867–870, 1999.
[47] R. H. Koch, J. A. Katine, and J. Z. Sun, “Time-Resolved Reversal of Spin-Transfer Switching in a Nanomagnet,” Phys. Rev. Lett., vol. 92, p. 088302, 2004.
[48] Y. Huai, F. Albert, P. Nguyen, M. Pakala, and T. Valet, “Observation of Spin-Transfer Switching in Deep Submicron-Sized and Low-Resistance Magnetic Tunnel Junctions,” Appl. Phys. Lett., vol. 84, pp. 3118–3120, 2004.
[49] M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachinoa, C. Fukumoto, H. Nagao, and H. Kano, “A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM,” Tech. Dig. - Int. Electron Devices Meet. (IEDM), pp. 459–462, 2005.
[50] W. H. Kautz, “Cellular Logic-in-Memory Arrays,” IEEE Trans. Comput., vol. 100, pp. 719–727, 1969.
[51] J. G. Wang, H. Meng, and J. P. Wang, “Programmable Spintronics Logic Device Based on a Magnetic Tunnel Junction Element,” J. Appl. Phys., vol. 97, p. 10D509, 2005.
[52] W. Zhao, E. Belhaire, C. Chappert, F. Jacquet, and P. Mazoyer, “New Non-Volatile Logic Based on Spin-MTJ,” Phys. Status Solidi (a), vol. 205, pp. 1373–1377, 2008.
[53] S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, H. Hasegawa, T. Endoh, H. Ohno, and T. Hanyu, “Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions,” Appl. Phys. Express, vol. 1, p. 091301, 2008.
[54] A. Lyle, J. Harms, S. Patil, X. Yao, D. Lilja, and J. P. Wang, “Direct Communication Between Magnetic Tunnel Junctions for Nonvolatile Logic Fan-out Architecture,” Appl. Phys. Lett., vol. 97, p. 152504, 2010.
[55] A. Lyle, S. Patil, J. Harms, B. Glass, X. Yao, D. Lilja, and J. P. Wang, “Magnetic Tunnel Junction Logic Architecture for Realization of Simultaneous Computation and Communication,” IEEE Trans. Magn., vol. 47, pp. 2970–2973, 2011.
[56] D. E. Nikonov, G. I. Bourianoff, , and T. Ghan, “Proposal of a Spin Torque Majority Gate Logic,” IEEE Electron Device Lett., vol. 32, pp. 1128–1130, 2011.
[57] Y. Gang, W. Zhao, J. O. Klein, C. Chappert, and P. Mazoyer, “A High-Reliability, Low-Power Magnetic Full Adder,” IEEE Trans. Magn., vol. 47, pp. 4611–4616, 2011.
[58] X. Yao, J. Harms, A. Lyle, F. Ebrahimi, Y. Zhang, and J. P. Wang, “Magnetic Tunnel Junction-Based Spintronic Logic Units Operated by Spin Transfer Torque,” IEEE Trans. Nanotechnol., vol. 11, pp. 120–126, 2012.
[59] M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu, “Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating,” Proceedings of the International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 194–195, 2013.
[60] Y. V. Pershin and M. D. Ventra, “Spin Memristive Systems: Spin Memory Effects in Semiconductor Spintronics,” Phys. Rev. B, vol. 78, p. 113309, 2008.
[61] X. Wang, Y. Chen, H. Xi, H. Li, and D. Dimitrov, “Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion,” IEEE Electron Device Lett., vol. 30, pp. 294–297, 2009.
[62] P. Krzysteczko, G. Reiss, and A. Thomas, “Memristive Switching of MgO Based Magnetic Tunnel Junctions,” Appl. Phys. Lett., vol. 95, p. 112508, 2009.
[63] H.-J. Jang, O. A. Kirillov, O. D. Jurchescu, and C. A. Richter, “Spin Transport in Memristive Devices,” Appl. Phys. Lett., vol. 100, p. 043510, 2012.
[64] A. Chanthbouala, R. Matsumoto, J. Grollier, V. Cros, A. Anane, A. Fert, A. V. Khvalkovskiy, K. A. Zvezdin, K. Nishimura, Y. Nagamine, H. Maehara, K. Tsunekawa, A. Fukushima, and S. Yuasa, “Vertical-Current-Induced Domain-Wall Motion in MgO-Based Magnetic Tunnel Junctions with Low Current Densities,” Nat. Phys., vol. 7, pp. 626–630, 2011.
[65] J. Grollier, A. Chanthbouala, R. Matsumoto, A. Anane, V. Cros, F. N. van Dau, and A. Fert, “Magnetic Domain Wall Motion by Spin Transfer,” Comptes Rendus Physique, vol. 12, pp. 309–317, 2011.
[66] W. Cai, T. Schmidt, U. Jorges, and F. Ellinger, “A Feedback Spin-Valve Memristive System,” IEEE Trans. Circuits Syst. I, vol. 59, pp. 2405–2412, 2012.
[67] Q. Li, T.-T. Shen, Y.-L. Cao, K. Zhang, S.-S. Yan, Y.-F. Tian, S.-S. Kang, M.-W. Zhao, Y.-Y. Dai, Y.-X. Chen, G.-L. Liu, L.-M. Mei, X.-L. Wang, and P. Grünberg, “Spin Memristive Magnetic Tunnel Junctions with CoO-ZnO Nano Composite Barrier,” Scientific Reports, vol. 4, p. 3835, 2014.
[68] L. O. Chua, “Memristor-The Missing Circuit Element,” IEEE Trans. Circuit Theory, vol. 18, pp. 507–519, 1971.
[69] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The Missing Memristor Found,” Nature, vol. 453, no. 7191, pp. 80–83, 2008.
[70] L. O. Chua and S. M. Kang, “Memristive Devices and Systems,” Proceedings of the IEEE, vol. 64, pp. 209–223, 1976.
[71] L. O. Chua, “Resistance Switching Memories are Memristors,” Appl. Phys. A, vol. 102, no. 4, pp. 765–783, 2011.
[72] ——, “If Its Pinched It’s a Memristor,” in Memristors and Memristive Systems. Springer New York, 2014, pp. 17–90.
[73] Q. Xia, W. Robinett, M. W. Cumbie, N. Banerjee, T. J. Cardinali, J. J. Yang, W. Wu, X. Li, W. M. Tong, D. B. Strukov, G. S. Snider, G. Medeiros-Ribeiro, and R. S. Williams, “Memristor-CMOS Hybrid Integrated Circuits for Reconfigurable Logic,” Nano Lett., vol. 9, pp. 3640–3645, 2009.
[74] J. Borghetti, Z. Li, J. Straznicky, X. Li, D. A. Ohlberg, W. Wu, D. R. Stewart, and R. S. Williams., “A Hybrid Nanomemristor/Transistor Logic Circuit Capable of Self-Programming,” Proc. of the Natl. Acad. of Sci., vol. 106, pp. 1699–1703, 2009.
[75] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, “Memristive Switches Enable Stateful Logic Operations via Material Implication,” Nature, vol. 464, pp. 873–876, 2010.
[76] X. Sun, G. Li, L. Ding, N. Yang, and W. Zhang, “Unipolar Memristors Enable Stateful Logic Operations via Material Implication,” Appl. Phys. Lett., vol. 99, p. 072101, 2011.
[77] S. Shin, K. Kim, and S. Kang, “Reconfigurable Stateful NOR Gate for Large-Scale Logic-Array Integrations,” IEEE Trans. Circuits Syst. II, vol. 58, pp. 442–446, 2011.
[78] S. Shin, K. Kim, and S.-M. Kang, “Memristive XOR for Resistive Multiplier,” Electron. Lett., vol. 48, pp. 78–80, 2012.
[79] J. Rajendran, H. Manem, R. Karri, and G. S. Rose, “An Energy-Efficient Memristive Threshold Logic Circuit,” IEEE Trans. Comput., vol. 61, pp. 474–487, 2012.
[80] S. Shin, K. Kim, and S.-M. Kang, “Resistive Computing: Memristors-Enabled Signal Multiplication,” IEEE Trans. Circuits Syst. I, vol. 60, pp. 1241–1249, 2013.
[81] J. J. Yang, D. B. Strukov, and D. R. Stewart, “Memristive Devices for Computing,” Nat. Nanotechnol., vol. 8, pp. 13–24, 2013.
[82] D. Fan, M. Sharad, and K. Roy, “Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic,” arXiv preprint arXiv:1402.2648, 2014.
[83] Y. V. Pershin, S. L. Fontaine, and M. D. Ventra, “Memristive Model of Amoeba Learning,” Phys. Rev. E, vol. 80, no. 2, p. 021926 (6 pp), 2009.
[84] Y. V. Pershin and M. D. Ventra, “Experimental Demonstration of Associative Memory with Memristive Neural Networks,” Neur. Netw., vol. 23, pp. 881–886, 2010.
[85] S. Jo, T. Chang, I. Ebong, B. Bhadviya, P. Mazumder, and W. Lu, “Nanoscale Memristor Device as Synapse in Neuromorphic Systems,” Nano Lett., vol. 10, pp. 1297–1301, 2010.
[86] P. Krzysteczko, J. Münchenberger, M. Schäfers, G. Reiss, and A. Thomas, “The Memristive Magnetic Tunnel Junction as a Nanoscopic Synapse-Neuron System,” Adv. Mater., vol. 24, pp. 762–766, 2012.
[87] R. Kozma, R. E. Pino, and G. E. Pazienza, Advances in Neuromorphic Memristor Science and Applications. Springer New York, 2012.
[88] F. Alibart, S. Pleutin, O. Bichler, C. Gamrat, T. Serrano-Gotarredona, B. Linares-Barranco, and D. Vuillaume, “A Memristive Nanoparticle/Organic Hybrid Synapstor for Neuroinspired Computing,” Adv. Func. Mater., vol. 22, pp. 609–616, 2012.
[89] G. D. Howard, L. Bull, B. D. L. Costello, E. Gale, and A. Adamatzky, “Evolving Memristive Neural Networks,” in Memristor Networks. Springer International Publishing, 2014, pp. 293–322.
[90] Y. Chen, H. Li, and Z. Sun, “Spintronic Memristor as Interface Between DNA and Solid State Devices,” in Memristors and Memristive Systems. Springer New York, 2014, pp. 281–298.
[91] Y. N. Joglekar and S. J. Wolf, “The Elusive Memristor: Properties of Basic Electrical Circuits,” Eur. J. Phys., vol. 30, pp. 661–675, 2009.
[92] Y. V. Pershin, E. Sazonov, and M. D. Ventra, “Analogue-to-Digital and Digital-to-Analogue Conversion with Memristive Devices,” Electron. Lett., vol. 48, pp. 73–74, 2012.
[93] A. Ascoli, R. Tetzlaff, F. Corinto, M. Mirchev, and M. Gilli, “Memristor-Based Filtering Applications,” Proceedings of the 14th IEEE Latin-American Test Workshop, pp. 1–6, 2013.
[94] X. Wang, Y. Chen, G. Ying, and H. Li, “Spintronic Memristor Temperature Sensor,” IEEE Electron Device Lett., vol. 31, pp. 20–22, 2010.
[95] X. Bi, C. Zhang, H. Li, Y. Chen, and R. E. Pino, “Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference,” Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 1301–1306, 2012.
[96] X. Wang and Y. Chen, “Spintronic Memristor Devices and Application,” Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 667–672, 2010.
[97] M. Itoh and L. O. Chua, “Memristor Oscillators,” Int. J. Bifu. Chaos, vol. 18, pp. 3183–3206, 2008.
[98] B. Mouttet, “Proposal for Memristors in Signal Processing,” In Nano-net 2008, vol. 58, pp. 11–13, 2009.
[99] S. Shin, K. Kim, and S. Kang, “Memristor-Based Fine Resolution Programmable Resistance and its Applications,” Proceedings of the International Conference on Communications, Circuits and Systems, pp. 948–951, 2009.
[100] Y. V. Pershin and M. D. Ventra, “Practical Approach to Programmable Analog Circuits With Memristors,” IEEE Trans. Circuits Syst. I, vol. 57, pp. 1857–1864, 2010.
[101] H. H.-C. Iu, D. S. Yu, A. L. Fitch, V. Sreeram, and H. Chen, “Controlling Chaos in a Memristor Based Circuit Using a Twin-T Notch Filter,” IEEE Trans. Circuits Syst. I, vol. 58, pp. 1337–1344, 2011.
[102] T. Wey and W. Jemison, “An Automatic Gain Control Circuit with TiO Memristor Variable Gain Amplifier,” Anal. Dig. Sign. Proc., vol. 73, pp. 663–672, 2012.
[103] F. Argall, “Switching Phenomena in Titanium Oxide Thin Films,” Solid-State Electron., vol. 11, pp. 535–541, 1968.
[104] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, I. K. Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, , and B. H. Park, “Reproducible Resistance Switching in Polycrystalline NiO Films,” Appl. Phys. Lett., vol. 85, pp. 5655–5657, 2004.
[105] B. J. Choi, D. S. Jeong, S. K. Kim, C. Rohde, S. Choi, J. H. Oh, H. J. Kim, C. S. Hwang, K. Szot, R. Waser, B. Reichenberg, and S. Tiedke, “Resistive Switching Mechanism of TiO Thin Films Grown by Atomic-Layer Deposition,” J. Appl. Phys., vol. 98, p. 033715, 2005.
[106] K. Szot, W. Speier, G. Bihlmayer, and R. Waser, “Switching the Electrical Resistance of Individual Dislocations in Single-Crystalline SrTiO,” Nat. Mater., vol. 5, pp. 312–320, 2006.
[107] B. J. Choi, J. J. Yang, M.-X. Zhang, K. J. Norris, D. A. A. Ohlberg, N. P. Kobayashi, G. Medeiros-Ribeiro, and R. S. Williams, “Nitride Memristors,” Appl. Phys. A, vol. 109, pp. 1–4, 2012.
[108] Z. Wang, P. B. Griffin, J. McVittie, S. Wong, P. C. McIntyre, and Y. Nishi, “Resistive Switching Mechanism in ZnCdS Nonvolatile Memory Devices,” IEEE Electron Device Lett., vol. 28, pp. 14–16, 2007.
[109] T. Sakamoto, K. Lister, N. Banno, T. Hasegawa, K. Terabe, and M. Aono, “Electronic Transport in TaO Resistive Switch,” Appl. Phys. Lett., vol. 91, p. 092110, 2007.
[110] W. Guan, M. Liu, S. Long, Q. Liu, and W. Wang, “On the Resistive Switching Mechanisms of Cu/ZrO:Cu/Pt,” Appl. Phys. Lett., vol. 93, p. 223506, 2008.
[111] C. Chen, Y. C. Yang, F. Zeng, and F. Pan, “Bipolar Resistive Switching in Cu/AlN/Pt Nonvolatile Memory Device,” Appl. Phys. Lett., vol. 97, p. 083502, 2010.
[112] R. Huang, L. Zhang, D. Gao, Y. Pan, S. Qin, P. Tang, Y. Cai, and Y. Wang, “Resistive Switching of Silicon-Rich-Oxide Featuring High Compatibility with CMOS Technology for 3D Stackable and Embedded Applications,” Appl. Phys. A, vol. 102, pp. 927–931, 2011.
[113] W. Lu, D. S. Jeong, M. Kozicki, and R. Waser, “Electrochemical Metallization Cells-Blending Nanoionics into Nanoelectronics?” Mater. Res. Soc. Bull., vol. 37, pp. 124–130, 2012.
[114] J. J. Yang, M. D. Pickett, X. Li, D. A. Ohlberg, D. R. Stewart, and R. S. Williams, “Memristive Switching Mechanism for Metal/Oxide/Metal Nanodevices,” Nat. Nanotechnol., vol. 3, pp. 429–433, 2008.
[115] J. Münchenberger, G. Reiss, and A. Thomas, “A Memristor Based on Current-Induced Domain-Wall Motion in a Nanostructured Giant Magnetoresistance Device,” J. Appl. Phys., vol. 111, p. 07D303, 2012.
[116] A. Chanthbouala, V. Garcia, R. O. Cherifi, K. Bouzehouane, S. Fusil, X. Moya, S. Xavier, H. Yamada, C. Deranlot, N. D. Mathur, M. Bibes, A. Barthélémy, and J. Grollier, “A Ferroelectric Memristor,” Nat. Mater., vol. 11, pp. 860–864, 2012.
[117] T. Driscoll, H.-T. Kim, B.-G. Chae, M. D. Ventra, and D. N. Basov, “Phase-Transition Driven Memristive System,” Appl. Phys. Lett., vol. 95, p. 043503, 2009.
[118] H.-S. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, “Phase Change Memory,” Proceedings of the IEEE, vol. 98, pp. 2201–2227, 2010.
[119] A. Ukil, “Memristance View of Piezoelectricity,” IEEE Sensors J., vol. 11, pp. 2514–2517, 2011.
[120] F. Meng, L. Jiang, K. Zheng, C. F. Goh, S. Lim, H. H. Hng, J. Ma, F. Boey, and X. Chen, “Protein-Based Memristive Nanodevices,” Small, vol. 7, pp. 3016–3020, 2011.
[121] A. W. Bushmaker, C.-C. Chang, V. V. Deshpande, M. Amer, M. W. Bockrath, and S. B. Cronin, “Memristive Behavior Observed in a Defected Single-Walled Carbon Nanotube,” IEEE Trans. Nanotechnol., vol. 10, pp. 582–586, 2011.
[122] E. Kyriakides, C. Hadjistassou, and J. Georgiou, “A New Memristor Based on NiTi Smart Alloys,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1403–1406, 2012.
[123] J. Georgiou, E. Kyriakides, and C. Hadjistassou, “NiTi Smart Alloys for Memristors with Multi-Time-Scale Volatility,” Electron. Lett., vol. 48, pp. 877–879, 2012.
[124] F. Corinto, A. Ascoli, and M. Gilli, “A Novel Elementary Memristive System,” Proceedings of the 20st IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), pp. 76–81, 2012.
[125] D. Liu, H. Cheng, X. Zhu, G. Wang, and N. Wang, “Analog Memristors Based on Thickening/Thinning of Ag Nanofilaments in Amorphous Manganite Thin Films,” ACS Appl. Mater. Interfaces, vol. 5, pp. 11 258–11 264, 2013.
[126] A. Emboras, I. Goykhman, B. Desiatov, N. Mazurski, L. Stern, J. Shappir, and U. Levy, “Nanoscale Plasmonic Memristor with Optical Readout Functionality,” Nano Lett., vol. 13, pp. 6151–6155, 2013.
[127] D. Sacchetto, Y. Leblebici, and G. D. Micheli, “Silicon Nanowire-Based Memristive Devices,” in Memristors and Memristive Systems. Springer New York, 2014, pp. 253–280.
[128] M. Yang, N. Qin, L. Z. Ren, Y. J. Wang, K. G. Yang, F. M. Yu, W. Q. Zhou, S. X. W. M. Meng, D. H. Bao, and S. W. Li, “Realizing a Family of Transition-Metal-Oxide Memristors Based on Volatile Resistive Switching at a Rectifying Metal/Oxide Interface,” J. of Phys. D: Appl. Phys., vol. 47, p. 045108, 2014.
[129] S. Benderli and T. A. Wey, “On SPICE Macromodelling of TiO Memristors,” Electron. Lett., vol. 45, pp. 377–379, 2009.
[130] Ádam Rák and G. Cserey, “Macromodelling of the Memristor in SPICE,” IEEE Trans. Computer-Aided Design, vol. 29, pp. 632–636, 2010.
[131] V. Biolkova, Z. Kolka, Z. Biolek, and D. Biolek, “Memristor Modeling Based on Its Constitutive Relation,” Proceedings of the European Conference of Systems, and European Conference of Circuits Technology and Devices, and European Conference of Communications, and European Conference on Computer Science, pp. 261–264, 2010.
[132] S. Shin, K. Kim, and S. Kang, “Compact Models for Memristors Based on Charge-Flux Constitutive Relationships,” IEEE Trans. Computer-Aided Design, vol. 29, pp. 590–598, 2010.
[133] D. Batas and H. Fiedler, “A Memristor SPICE Implementation and a New Approach for Magnetic Flux-Controlled Memristor Modeling,” IEEE Trans. Nanotechnol., vol. 10, pp. 250–255, 2011.
[134] J. T. Diao and X. B. Tian, “A Simulation Method for Memristor Based Dopant Drift Model,” Appl. Mechan. and Mater., vol. 239, pp. 915–920, 2013.
[135] Y. Chen and X. Wang, “Compact Modeling and Corner Analysis of Spintronic Memristor,” Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, pp. 7–12, 2009.
[136] H. H. Li and M. Hu, “Compact Model of Memristors and Its Application in Computing Systems,” Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 673–678, 2010.
[137] M. Hu, H. Li, Y. Chen, X. Wang, and R. Pino, “Geometry Variations Analysis of Thin-Film and Spintronic Memristors,” ASP-DAC, pp. 23–30, 2011.
[138] M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R. Stewart, and R. S. Williams, “Switching Dynamics in Titanium Dioxide Memristive Devices,” J. Appl. Phys., vol. 106, p. 074508, 2009.
[139] H. Abdalla and M. D. Pickett, “SPICE Modeling of Memristors,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1832–1835, 2011.
[140] F. Z. Wang, N. Helian, S. Wu, M.-G. Lim, Y. Guo, and M. A. Parker, “Delayed Switching in Memristors and Memristive Systems,” IEEE Electron Device Lett., vol. 31, pp. 755–757, 2010.
[141] C. Yakopcic, T. M. Taha, G. Subramanyam, R. E. Pino, and S. Rogers, “A Memristor Device Model,” IEEE Electron Device Lett., vol. 32, pp. 1436–1438, 2011.
[142] S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “TEAM: ThrEshold Adaptive Memristor Model,” IEEE Trans. Circuits Syst. I, vol. 60, pp. 211–221, 2013.
[143] Y. V. Pershin and M. D. Ventra, “SPICE Model of Memristive Devices with Threshold,” Radioengineering, no. 2, 2013.
[144] S. H. Jo, K.-H. Kim, and W. Lu, “Programmable Resistance Switching in Nanoscale Two-Terminal Devices,” Nano Lett., vol. 9, pp. 496–500, 2008.
[145] S. C. Chae, J. S. Lee, S. Kim, S. B. Lee, S. H. Chang, C. Liu, B. Kahng, H. Shin, D.-W. Kim, C. U. Jung, S. Seo, M.-J. Lee, and T. W. Noh, “Random Circuit Breaker Network Model for Unipolar Resistance Switching,” Adv. Mater., vol. 20, pp. 1154–1159, 2008.
[146] R. L. McCreery and A. J. Bergren, “Progress with Molecular Electronic Junctions: Meeting Experimental Challenges in Design and Fabrication,” Adv. Mater., vol. 21, pp. 4303–4322, 2009.
[147] D. B. Strukov, J. L. Borghetti, and R. S. Williams, “Protein-Based Memristive Nanodevices,” Small, vol. 5, pp. 1058–1063, 2009.
[148] D. Strukov and R. S. Williams, “Exponential Ionic Drift: Fast Switching and Low Volatility of a Thin-Film Memristors,” Appl. Phys. A, vol. 94, pp. 515–519, 2009.
[149] G. Medeiros-Ribeiro, F. Perner, R. Carter, H. Abdalla, M. D. Pickett, and R. S. Williams, “Lognormal Switching Times for Titanium Dioxide Bipolar Memristors: Origin and Resolution,” Nanotechnol., vol. 22, p. 095702, 2011.
[150] J. J. Yang, F. Miao, M. D. Pickett, D. A. Ohlberg, D. R. Stewart, C. N. Lau, and R. S. Williams, “The Mechanism of Electroforming of Metal Oxide Memristive Switches,” Nanotechnol., vol. 20, p. 215201, 2009.
[151] N. Gergel-Hackett, B. Hamadani, B. Dunlap, J. Suehle, C. Richter, C. Hacker, and D. Gundlach, “A Flexible Solution-Processed Memristor,” IEEE Electron Device Lett., vol. 30, pp. 706–708, 2009.
[152] D.-H. Kwon, K. M. Kim1, J. H. Jang, J. M. Jeon, M. H. Lee, G. H. Kim, X.-S. Li, G.-S. Park, B. Lee, S. Han, M. Kim, and C. S. Hwang, “Atomic Structure of Conducting Nanofilaments in TiO Resistive Switching Memory,” Nat. Nanotechnol., vol. 5, pp. 148–153, 2010.
[153] J. P. Strachan, M. D. Pickett, J. J. Yang, S. Aloni, A. L. D. Kilcoyne, G. Medeiros-Ribeiro, and R. S. Williams, “Direct Identification of the Conducting Channels in a Functioning Memristive Device,” Adv. Mater., vol. 22, pp. 3573–3577, 2010.
[154] F. Miao, J. J. Yang, J. Borghetti, G. Medeiros-Ribeiro, and R. S. Williams, “Observation of Two Resistance Switching Modes in TiO Memristive Devices Electroformed at Low Current,” Nanotechnol., vol. 22, p. 254007, 2011.
[155] J. L. Tedesco, L. Stephey, M. Hernandez-Mora, C. A. Richter, and N. Gergel-Hackett, “Switching Mechanisms in Flexible Solution-Processed TiO Memristors,” Nanotechnol., vol. 23, p. 305206, 2012.
[156] Z. Fan, X. Fan, A. Li, and L. Dong, “In Situ Forming, Characterization, and Transduction of Nanowire Memristors,” Nanoscale, vol. 5, pp. 12 310–12 315, 2013.
[157] Y. Yang and W. Lu, “Nanoscale Resistive Switching Devices: Mechanisms and Modeling,” Nanoscale, vol. 5, pp. 10 076–10 092, 2013.
[158] M. K. Hota, M. K. Bera, and C. K. Maiti, “Switching Mechanism in Au Nanodot-Embedded NbO Memristors,” J. Nanosc. Nanotech., vol. 14, pp. 3538–3544, 2014.
[159] G. J. Simmons, “Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film,” J. Appl. Phys., vol. 34, pp. 1793–1803, 1963.
[160] A. Whitehead and B. Russell, Principia Mathematica. Cambridge at the University Press, 1910.
[161] C. E. Shannon, A Symbolic Analysis of Relay and Switching Circuits. Master’s thesis, MIT, 1940.
[162] S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-based IMPLY Logic Design Procedure,” Proc. IEEE Int. Conf. Comput. Design, pp. 142–147, 2011.
[163] Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii, K. Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, I. Takagi, R. Yasuhara, K. Horiba, H. Kumigashira, and M. Oshim, “Highly Reliable TaO ReRAM and Direct Evidence of Fedox Reaction Mechanism,” Tech. Dig. - Int. Electron Devices Meet. (IEDM), p. 293, 2008.
[164] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-Based Resistive Switching Memories-Nanoionic Mechanisms, Prospects, and Challenges,” Adv. Mater., vol. 21, pp. 2632–2663, 2009.
[165] A. Chung, J. Deen, J.-S. Lee, and M. Meyyappan, “Nanoscale Memory Devices,” Nanotechnol., vol. 21, p. 412001, 2010.
[166] J. J. Yang, M.-X. Zhang, J. P. Strachan, F. Miao, M. D. Pickett, R. D. Kelley, G. Medeiros-Ribeiro, and R. S. Williams, “High Switching Endurance in TaOx Memristive Devices,” Appl. Phys. Lett., vol. 97, p. 232102, 2010.
[167] N. Savage, IEEE Spectrum, 2009. [Online]. Available: http://spectrum.ieee.org/semiconductors/devices/spintronic-memristors/
[168] W. Zhao, C. Chappert, V. Javerliac, and J.-P. Nozie, “High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits,” IEEE Trans. Magn., vol. 45, pp. 3784–3787, 2009.
[169] M. Julliere, “Tunneling Between Ferromagnetic Films,” Phys. Lett. A, vol. 54, pp. 225–226, 1975.
[170] G. Tatara and H. Kohno, “Theory of Current-Driven Domain Wall Motion: Spin Transfer Versus Momentum Transfer,” Phys. Rev. Lett., vol. 92, p. 086601, 2004.
[171] A. Yamaguchi, T. Ono, S. Nasu, K. Miyake, K. Mibu, and T. Shinjo, “Real-Space Observation of Current-Driven Domain Wall Motion in Submicron Magnetic Wires,” Phys. Rev. Lett., vol. 92, p. 077205, 2004.
[172] L. Berger, “Analysis of Measured Transport Properties of Domain Walls in Magnetic Nanowires and Films,” Phys. Rev. B, vol. 73, p. 014407, 2006.
[173] M. Hayashi, L. Thomas, C. Rettner, R. Moriya, Y. B. Bazaliy, and S. S. P. Parkin, “Current Driven Domain Wall Velocities Exceeding the Spin Angular Momentum Transfer Rate in Permalloy Nanowires,” Phys. Rev. Lett., vol. 98, p. 037204, 2007.
[174] A. Thiaville, Y. Nakatani, J. Miltat, and Y. Suzuki, “Micromagnetic Understanding of Current-Driven Domain Wall Motion in Patterned Nanowires,” Europhys. Lett., vol. 69, p. 990, 2005.
[175] L. Thomas and S. Parkin, “Current Induced Domain-wall Motion in Magnetic Nanowires,” in Handbook of Magnetism and Advanced Magnetic Materials. Wiley Online Library, 2007, pp. 1–41.
[176] T. Koyama, D. Chiba, K. Ueda, K. Kondou, H. Tanigawa, S. Fukami, T. Suzuki, N. Ohshima, N. Ishiwata, Y. Nakatani, K. Kobayashi, and T. Ono, “Observation of the Intrinsic Pinning of a Magnetic Domain Wall in a Ferromagnetic Nanowire,” Nat. Mater., vol. 10, pp. 194–197, 2011.
[177] J. Shibata, G. Tatara, and H. Kohno, “A Brief Review of Field-and Current-Driven Domain-Wall Motion,” J. of Phys. D: Appl. Phys., vol. 44, p. 384004, 2011.
[178] W. F. Brown, “Thermal Fluctuations of a Single-Domain Particle,” Phys. Rev., vol. 130, pp. 1677–1686, 1963.
[179] J. Ryu and H. W. Lee, “Current-Induced Domain Wall Motion: Domain Wall Velocity Fluctuations,” J. Appl. Phys., vol. 105, pp. 093 929–093 929, 2009.
[180] R. A. Duine, A. S. Nunez, and A. H. MacDonald, “Thermally Assisted Current-Driven Domain-Wall Motion,” Phys. Rev. Lett., vol. 98, p. 056605, 2007.
[181] Everspin Technologies. [Online]. Available: http://www.everspin.com/spinTorqueMRAM.php
[182] S. Ikeda, J. Hayakawa, Y. Ashizawa, Y. M. Lee, K. Miura, H. Hasegawa, M. Tsunoda, F. Matsukura, and H. Ohno, “Tunnel Magnetoresistance of 604% at 300 K by Suppression of Ta Diffusion in CoFeB/MgO/CoFeB Pseudo-Spin-Valves Annealed at High Temperature,” Appl. Phys. Lett., vol. 93, p. 082508, 2008.
[183] W. H. Butler, X.-G. Zhang, T. C. Schulthess, and J. M. MacLaren, “Spin-Dependent Tunneling Conductance of FeMgOFe Sandwiches,” Phys. Rev. B, vol. 63, p. 054416, 2001.
[184] J. Mathon and A. Umersky, “Theory of Tunneling Magnetoresistance of an Epitaxial Fe/MgO/Fe(001) Junction,” Phys. Rev. B, vol. 63, p. 220403, 2001.
[185] Z. Diao, M. Pakala, A. Panchula, Y. Ding, D. Apalkov, L.-C. Wang, E. Chen, and Y. Huai, “Spin-Transfer Switching in MgO-Based Magnetic Tunnel Junctions,” J. Appl. Phys., vol. 99, p. 08G510, 2006.
[186] Z. M. Zeng, P. K. Amiri, G. Rowlands, H. Zhao, I. N. Krivorotov, J.-P. Wang, J. A. Katine, J. Langer, K. Galatsis, K. L. Wang, , and H. W. Jiang, “Effect of Resistance-Area Product on Spin-Transfer Switching in MgO-Based Magnetic Tunnel Junction Memory Cells,” Appl. Phys. Lett., vol. 98, p. 072512, 2011.
[187] H. Kronmüller, “General Micromagnetic Theory,” Handbook of Magnetism and Advanced Magnetic Materials, 2007.
[188] J. D. Harms, F. Ebrahimi, X. F. Yao, and J. P. Wang, “SPICE Macromodel of Spin-Torque-Transfer-Operated Magnetic Tunnel Junctions,” IEEE Trans. Electron Devices, vol. 57, pp. 1425–1430, 2010.
[189] Y. Higo, K. Yamane, K. Ohba, H. Narisawa, K. Bessho, M. Hosomi, and H. Kano, “Thermal Activation Effect on Spin Transfer Switching in Magnetic Tunnel Junctions,” Appl. Phys. Lett., vol. 87, p. 082502, 2005.
[190] Y. Zhang, W. Zhao, Y. Lakys, J. O. Klein, J. V. Kim, D. Ravelosona, and C. Chappert, “Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions,” IEEE Trans. Electron Devices, vol. 59, pp. 819–826, 2012.
[191] R. Beach, T. Min, C. Horng, Q. Chen, P. Sherman, S. Le, S. Young, K. Yang, H. Yu, X. Lu, W. Kula, T. Zhong, R. Xiao, A. Zhong, G. Liu, J. Kan, J. Yuan, J. Chen, R. Tong, J. Chien, T. Torng, D. Tang, P. Wang, M. Chen, S. Assefa, M. Qazi, J. DeBrosse, M. Gaidis, S. Kanakasabapathy, Y. Lu, J. Nowak, E. O’Sullivan, T. Maffitt, J. Sun, and W. Gallagher, “A Statistical Study of Magnetic Tunnel Junctions for High-Density Spin Torque Transfer-MRAM (STT-MRAM),” Tech. Dig. - Int. Electron Devices Meet. (IEDM), pp. 306–308, 2008.
[192] W. Zhao, L. Torres, Y. Guillemenet, L. V. Cargnini, Y. Lakys, J.-O. Klein, D. Ravelosona, G. Sassatelli, and C. Chappert, “Design of MRAM based Logic Circuits and its Applications,” in ACM Great Lakes Symposium on VLSI, 2011, pp. 431–436.
[193] B. Razavi, Fundamentals of Microelectronics. Wiley, 2006.
[194] E. Lehtonen, J. H. Poikonen, and M. Laiho, “Two Memristors Suffice to Compute All Boolean Functions,” Electron. Lett., vol. 46, pp. 239–240, 2010.
[195] J. Shen, “Logic Devices and Circuits Based on Giant Magnetoresistance,” IEEE Trans. Magn., vol. 33, pp. 4492–4497, 1997.
[196] R. Richter, L. Bar, J. Wecker, , and G. Reiss, “Nonvolatile Field Programmable Spin-Logic for Reconfigurable Computing,” Appl. Phys. Lett., vol. 80, p. 1291, 2002.
[197] H. Meng, J. G. Wang, and J. P. Wang, “A Spintronics Full Adder for Magnetic CPU,” IEEE Electron Device Lett., vol. 26, pp. 360–362, 2005.
[198] J. P. Wang and X. F. Yao, “Programmable Spintronic Logic Devices for Reconfigurable Computation and Beyond,” J. Nanoelectron. Optoelectron., vol. 3, pp. 12–23, 2008.
[199] L. Leem and J. S. Harris, “Magnetic Coupled Spin-Torque Devices for Nonvolatile Logic Applications,” J. Appl. Phys., vol. 105, p. 07D102, 2009.
[200] V. Höink, J. W. Lau, and W. F. Egelhoff, “Micromagnetic Simulations of a Dual-Injector Spin Transfer Torque Operated Spin Logic,” Appl. Phys. Lett., vol. 96, p. 142508, 2010.
[201] F. E. J. H. A. Lyle, X. F. Yao and J. P. Wang, “The 3-Bit Gray Counter Based on Magnetic-Tunnel-Junction Elements,” IEEE Trans. Magn., vol. 46, pp. 2216–2219, 2010.
[202] K. Bickerstaff and E. E. Swartzlander, “Memristor-Based Arithmetic,” Asilomar conf. on Sig., Sys., and Comp., pp. 1173–1177, 2010.
[203] S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, T. Endoh, H. Ohno, and T. Hanyu, “MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues,” Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 433–435, 2009.
[204] Y. Liu, S. Chen, M. Nakayama, and K. Watanabe, “Limitations of a Relaxation Oscillator in Capacitance Measurements,” IEEE Trans. Instrum. Meas., vol. 49, pp. 980–983, 2000.
[205] W. S. Snyder and D. V. Ess, “Capacitance Sensor Using Relaxation Oscillator,” Patent US 07 307 485 B1, 2007. [Online]. Available: http://www.lens.org/lens/patent/US_7307485_B1
[206] H. Nobumi and S. Takeo, “An RC Discharge Digital Capacitance Meter,” IEEE Trans. Instrum. Meas., vol. 32, pp. 316–321, 1983.
[207] Z. Albus, “PCB-Based Capacitive Touch Sensing With MSP430,” Texas Instruments, Dallas, Application Report SLAA363A, 2007. [Online]. Available: http://www.ti.com/lit/an/slaa363a/slaa363a.pdf
[208] “Capacitance and Inductance Measurements Using an Oscilloscope and a Function Generator,” Tektronix, Application Note, 2007. [Online]. Available: http://www.tek.com/document/application-note/capacitance-and-inductance-measurements-using-oscilloscope-and-function-ge
[209] C. Liguori, “Capacitance and Inductance Measurement,” in Handbook of Measuring System Design, 2005.
[210] S. Zhang and Z. Li, “Roles of Nonequilibrium Conduction Electrons on the Magnetization Dynamics of Ferromagnets,” Phys. Rev. Lett., vol. 93, p. 127204, 2004.
[211] E. D. Ranieri, P. E. Roy, D. Fang, E. K. Vehsthedt, A. C. Irvine, D. Heiss, A. Casiraghi, R. P. Campion, B. L. Gallagher, T. Jungwirth, and J. Wunderlich, “Piezoelectric Control of the Mobility of a Domain Wall Driven by Adiabatic and Non-Adiabatic Torques,” Nat. Mater., vol. 12, pp. 808–814, 2013.
[212] G. Tatara, H. Kohno, and J. Shibata, “Microscopic Approach to Current-Driven Domain Wall Dynamics,” Phys. Rep., vol. 468, pp. 213–301, 2008.
[213] C. Burrowes, A. P. Mihai, D. Ravelosona, J.-V. Kim, C. Chappert, L. Vila, A. Marty, Y. Samson, F. Garcia-Sanchez, L. D. Buda-Prejbeanu, I. Tudosa, E. E. Fullerton, and J.-P. Attane, “Non-Adiabatic Spin-Torques in Narrow Magnetic Domain Walls,” Nat. Phys., vol. 6, pp. 17–21, 2010.
[214] M. Eltschka, M. Wötzel, J. Rhensius, S. Krzyk, U. Nowak, M. Kläui, T. Kasama, R. E. Dunin-Borkowski, L. J. Heyderman, H. J. van Driel, and R. A. Duine, “Nonadiabatic Spin Torque Investigated Using Thermally Activated Magnetic Domain Wall Dynamics,” Phys. Rev. Lett., vol. 105, p. 056601, 2010.
[215] N. L. Schryer and L. R. Walker, “The Motion of 180 Domain Walls in Uniform DC Magnetic Fields,” J. Appl. Phys., vol. 45, pp. 5406–5421, 2003.
[216] A. Mougin, M. Cormier, J. P. Adam, P. J. Metaxas, and J. Ferré, “Domain Wall Mobility, Stability and Walker Breakdown in Magnetic Nanowires,” Europhys. Lett., vol. 78, p. 57007, 2007.
[217] J. Wunderlich, D. Ravelosona, C. Chappert, F. Cayssol, V. Mathet, J. Ferre, j. P Jamet, and A. Thiaville, “Influence of Geometry on Domain Wall Propagation in a Mesoscopic Wire,” IEEE Trans. Magn., vol. 37, pp. 2104–2107, 2001.