3.5  Summary

The realization of the stateful implication logic, a new kind of logic based on material implication which is computationally complete, provides zero-standby power for intrinsic logic-in-memory designs based on TiO memristive devices. In this chapter, studies on TiO-based memristive stateful logic gates are presented. As under high voltage regimes required for (relatively) high-speed computing (Fig. 3.10), the electron tunneling significantly affects the electrical behavior of the of TiO memristive devices, a nonlinear memristor model has been employed to analyze and optimize the TiO-based memristive stateful logic gates. The circuit parameters of the gate are optimized to ensure correct implication logic behavior and to minimize the state drift error accumulations for different input patterns. Simulation results based on the nonlinear memristor model show a good agreement with experimental observations and illustrate that, in order to avoid a state computation error, a refreshing is required after a limited number of logic steps (10–20 steps) as the state drift errors accumulate in sequential logic steps. This is very unfavorable as it needs extra hardware for refreshing and increases complexity. Furthermore, limited number of cycles for reversibly and reliably switching (so-called endurance) is still a major challenge for metal/oxide/metal technology to be used as universal memory cells or computing devices [163, 164, 165, 166]. Compared to the spintronic devices, TiO memristive switches exhibit at least three orders of magnitude lower endurance [81]. In addition, spintronic devices provide a very fine level of control and faster switching [167, 64] compared to the TiO memristive devices which exhibit a very low mobility of dopants (oxygen vacancies) in the TiO thin film [69].