In modern microelectronic devices the dominant memory types are dynamic random access memory (DRAM), static RAM (SRAM), and flash memory. These types of memory store data as a charge state. For many decades these memory technologies have been successfully scaled down to achieve higher speed and increased density of memory chips at lower bit cost [86]. However, memories based on charge storage are gradually approaching the physical limits of scalability.
Although a new cell structure for DRAM has been developed by industry to overcome the scaling challenges at 30nm, a future size reduction below 20nm is facing physical limitations and elevated process complexity resulting in high manufacturing cost. DRAM with vertical gate type transistors was introduced in order to resolve the critical scaling problems, but it is not easy to reduce the size of the cell capacitor for the 20nm technology node [86]. A DRAM memory cell based on a transistor alone technology could solve this problem. The ultimate advantage of this new concept is that it does not require a capacitor, and, in contrast to traditional 1T1C DRAM cells, it thus represents a 1T0C cell named zero-capacitance RAM (ZRAM).
The concept of a DRAM memory cell based on a transistor alone was introduced already a decade ago [5],[9],[10],[62],[81],[176],[210],[255]. The functionality of the first generation ZRAM is based on the possibility to store majority carriers in the floating body of a silicon on insulator (SOI) transistor. The carriers are generated by impact ionization caused by the minority carriers close to the drain. The threshold voltage is modified because of the charge accumulated in the body thus guaranteeing the two states of a MOSFET channel, open and close, for a gate voltage chosen between the two thresholds.
The idea of the second generation ZRAM is to exploit the properties of the parasitic bipolar transistor [175], allowing to expand the ZRAM applicability to such advanced non-planar devices as FinFETs, multiple gate FETs, and gate-all-around FETs. Contrary to the first generation ZRAM, the current is flowing through the body of the structure. This increases the value of current by roughly the ratio of the fin radius to the surface layer thickness. The majority carriers are generated due to impact ionization. They are stored under the gate at the silicon/silicon dioxide interface. The stored charge provides good control over the bipolar current, in contrast to the first generation ZRAM, where the charge is stored in the area close to the buried oxide.
While keeping all advantages of the first ZRAM generation, the most recent generation of ZRAM cells [175] is characterized by a significantly enlarged programming window and much longer retention times. In [223] it is demonstrated that the programming window, which is formed by the two current values and the two gate voltage values when switching appears, is sufficiently large for stable ZRAM operation on 50nm double-gate transistors. In 2008, a 128Mb floating body RAM was designed and developed [81].
The meta-stable dip RAM (MSDRAM) is based on the MSD hysteresis effect [11] in fully depleted (FD) transistors [12],[13]. State 1 differs from State 0 by the presence of majority carriers in the gate-to-drain/source regions, which in turn determines the current flow at the back channel. Majority carriers are generated by band-to-band tunneling [94].
To reduce the operating voltage, a new concept of a 1T0C cell for advanced RAM (ARAM) was proposed [183],[184],[186]. The ARAM structure is represented in a form of a FD SOI transistor with two ultrathin semibodies physically isolated by a middle oxide but sharing the source and drain regions [186]. Two separate semibodies allow to store the population of majority (holes) and minority (electrons) charges separately without triggering their recombination. The transition between State 1 and State 0, and vice versa, occurs due to charging and discharging the top (between gate and middle oxide) semibody by holes. The memory cell is programmed via impact ionization or band-to-band tunneling.
The physical separation of the channels leads to substantial operation flexibility and improved performance, but introduces additional complexity in the cell architecture [185]. To overcome this drawback, a second generation ARAM (A2RAM) was proposed [185],[187],[188],[189]. The new cell architecture used the electrical isolation of the two types of carriers by a vertical p-n junction.
Most of 1T0C memories use impact ionization or band-to-band tunneling for writing, leading to slow write speeds and requiring high operating voltage [237]. Recently, the zero subthreshold swing and zero impact ionization RAM (Z2RAM) was proposed and studied in details [235],[236],[237],[238],[239]. The Z2RAM is a forward-biased PIN diode, where the FD body is only partially covered by the gate [235].
Based on a 1T0C memory cell the concept of the unified memory (URAM) was proposed. The URAM combines a non-volatile memory and 1T0C memory cell [45]. Non-volatility is achieved through the integration of the charge trapping layer (tunneling oxide/nitride/blocking oxide). Electrons are injected and trapped in the silicon nitride layer like in a standard SONOS memory [45].
The next step in the evolution of memory concepts involves the development of universal memory. Future universal memory should combine not only the high density of DRAM with non-volatility (flash memory), but also possess the main advantages of other charge based memory types, i.e. include the high speed of SRAM [44]. Therefore development of conceptually new types of memories based on a different storage principle are gaining momentum. Apart from good scalability, high operation speed, long retention time, and non-volatility the new type of memory must also exhibit low operating voltage, low power consumption, high endurance, and a simple structure [137].
This thesis is devoted to the concepts of the emerging resistive memory technology. Modeling of the two classes of resistive memory, namely, based on the change of the ohmic resistance (RRAM) and on the change of the magnetoresistance (STT-MRAM) is especially considered. Thus, the document can be divided into two parts: Chapter 2 and 3 are devoted to the memory concepts based on the ohmic resistance, Chapters 4 through 8 are devoted to magnetoresistive memory.
Chapter 2 introduces ohmic resistive switching memory, describes the basic operation principles of this memory concept, the materials used, and identifies the main problems impeding its large-scale integration. In addition, Chapter 2 describes the mechanisms of resistive switching and the models representing them. Due to the high interest in this type of memory and the rapid development of modeling techniques, the modeling methods are divided into three stages: (i) first suggestions and early models; (ii) current research status; (iii) a proposal of a new stochastic model of resistive switching (Chapter 3).
Chapter 4 introduces the concept of magnetic memory, describes the current magnetoresistive memory technology, and focuses on the basic principles of operation and the nature of the phenomena of magnetoresistance changes (GMR and TMR). Furthermore, the basic architecture of the magnetoresistance memory cells are presented and the major problems are identified.
Chapter 5 describes the theoretical background of micromagnetic simulations. The discretization of the magnetic field and the solution of the magnetodynamic equations by the finite difference method are shown in Chapter 6.
Chapter 7 describes the main results of the magnetoresistive memory simulations and presents methods of memory cell structure optimization. Furthermore, Chapter 8 discusses the reliability issues and two concepts of spin-torque oscillators based on the found parasitic effect for the switching memory process are proposed.
Finally, in Chapter 9, the main results of the thesis are summarized.