3.1 VISTA's Layout Editor Basic Concepts

Since the final result of an integrated circuit design is layout data representing the mask artwork of the structures to be fabricated (or simulated), it is obvious that this information must be supplied to the TCAD framework, or in simple cases, generated there. Nevertheless, the tools used in TCAD frameworks to display and manipulate geometrical data are a priori not suitable to handle layout data. They have been developed to edit two-dimensional device geometries (vertical design) in which, for example, there are no overlapping polygons or support for layer names.

In VISTA, data is stored as Profile Interchange Format (PIF) [18] files. The tool PIF EDitor (PED) [19], used to enter and display device geometries, suffered the mentioned drawbacks and a new special editing mode - the ``layout mode'' had to be added to the existent ``material mode''.

Layout editors in TCAD environments do not need to be complex. Three-dimensional simulations require large quantities of memory and CPU time, which limits the layout sizes they can simulate to small pieces. This excludes the necessity of a tool with a powerful geometry edition/manipulation and hierarchy support. In [20] a ``little layout editor'' is described which is designed for interactive specification of a single transistor or gate. We extended the concept a bit further, yet keeping the editor as simple as possible. As a consequence, in the drawing mode, only arbitrarily shaped polygons are supported and primitives like circles must be approximated. Polygon stretching and label edition are also not allowed. In spite of these limitations, providing a simple, but functional user-interface, small layouts (with few 10s of transistors) can be edited easily and relatively fast. The program is simple to learn and requires little training to full productivity. This is important because technology specialists are usually not familiar with the powerful and heavy design interfaces found on commercial layout tools.

But if large layouts are needed, they can be edited elsewhere and imported to VISTA. The preferred layout data format for industry is Calma's GDSII [21], but in research institutes and universities the Caltech Interchange Format (CIF) is also used [22]. Converters from both these formats to PIF were included to allow VISTA to interface any external tool. In Figure 3.2 the layout of a 3 to 8 decoder in a $0.35\mu m$ technology is presented. It was imported from the DFW-II Cadence ECAD framework.

Figure 3.2: Layout example: A digital 3 to 8 decoder.

In a technology-file the editor can be customized to a specific technology. In this file the GDSII layer names, the draw color and textures of layers, and the rules to perform a a netlist extraction from the layout are also defined here.

Device simulators need to know biasing conditions to run and others, such as capacitance extractions simulators, must know which nets will be extracted. Therefore, contacts and net-names specifications are required. In PED both can be entered interactively and net-names can be automatically assigned, as well. When assigning contacts, the user can specify a voltage or a current density level and errors, like giving to the same net different names or contact voltages, are reported and corrected.

What we have presented above are common features in layout editors. They establish the minimum requirements for a usable layout editor. However, we have realized that some particularities not present in conventional layout editors are valuable in a TCAD framework which will be presented in the next sections.