As designers try to integrate complete systems into one chip and improve performance to levels never achieved before, new demands for ECAD tools arise. First, as the world is analog, complete systems need to include analog and digital circuits in the same die. These mixed-mode integrated circuits are much more difficult to design than two individual chips (one processing the analog information plus A/D conversion, and another completely digital). Secondly, very high performance digital circuits are reaching very high clock speeds and their critical parts must be simulated at a low level, or in other words, as being analog. Bearing these two considerations in mind, it becomes clear that new tools should overcome today's ECAD limitations in a reliable and accurate circuit level simulation of sub-micron transistors. Modeling substrate noise coupling, crosstalk between lines, propagation delays and other phenomena related to interconnection modeling are imperative requirements as well.
Although TCAD frameworks are not intended to be used in the design of a complete integrated circuit, they include some features and tools that can cover the topics described above and overcome the problems of classical ECAD tools.
The link between the designer and the fabrication facilities is the layout information. The same applies to ECAD and TCAD: As presented in Figure 3.1, the information about the location where the gate must be formed is given by the photo-mask generated from the layout. In this chapter we report on the concepts of how layout data was incorporated in the VISTA TCAD framework.
