7.1 Ring Oscillator Revisited

We presented the ring oscillator as a good benchmark circuit for technology optimization. In Chapter 5 we focused on the devices, and the simulations neglected the interconnect capacitances. Using the same process parameters we performed a three-dimensional topography simulation and extracted the node capacitances that were included in the circuit netlist. The circuit was then re-simulated and the new results compared with those obtained in Section 5.2.3.

Figure 7.2 shows the structure after depositing the inter-metal oxide and etching the contact openings. Figure 7.3 displays the final structure of the ring oscillator (to look into the conductors the SiO$_2$ material was removed). This structure contains 1.4 million elements and the total simulation time was 3 hours in a DEC 3000/400 workstation.

As we can see from Figure 7.1 that a drastic reduction in the oscillating frequency occurs due to the parasitic capacitors. The frequency decreased to 270MHz which corresponds to a reduction of about 25%. A better layout would avoid the interconnections between the gates of the same inverter in polysilicon. Although one extra contact per inverter would be necessary, this would improve the circuit speed by about 7.5%.

From this example, it becomes clear that the intrinsic relative fast switching times of the devices in this technology, require a careful layout and, for this case, interconnects with $0.35\mu m$ design rules would be the best choice.

Figure 7.1: Transient simulation of the ring oscillator with parasitic capacitances taken into account.

Figure 7.2: Ring oscillator's structure after contact opening.

Figure 7.3: Complete three-dimensional structure of the ring oscillator.