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The requirements on grids of process- and
device simulators are very different. On one hand the process
simulation grid has to follow steep gradients in the doping profile
and must resolve internal interfaces like / with an
accuracy sufficient to model segregation and dopant transport across
interfaces [124],[125]. Furthermore, it must be able to adapt to changes in the
boundary occurring during process steps like oxidation or
etching. These changes can lead even to topology changes (like etching
a hole through one layer converting one segment into two separated
segments) [87],[88],[126]. On the other hand the device
simulation grid must resolve mainly the fields of physical quantities
occurring during a device simulation, like carrier concentrations or
electrostatic potential. Thus
the grid obtained by the process simulation is normally not suitable to get
sufficiently accurate results for device simulations.
Therefore, re-meshing of the resulting structure after process
simulation is mandatory. Re-meshing is a very sensitive process, since
it includes interpolation of the dopant distributions on a new
grid [127],[128]. Care has to be taken, not to increase the errors in
the mesh representation of the dopant field [129]. Especially the
boundaries where currents occur during the device operation have to
represented appropriately by the mesh. A proper grid for carrier
transport simulation should follow the current flows during device
operation (like a refined channel in a MOS structure for simulation of
the transfer characteristics of a MOS device).
There are three strategies to generate a suitable grid. A straight
forward and very stable method is the generation of the grid based on dopant
gradient criteria. For certain applications
these methods have big disadvantages, because they do not generate a high
resolution in areas where necessary. For instance the channel,
of a MOS transistor shows no steep dopant gradient and is thus not well
resolved by a standard gradient criteria based grid. One workaround is to
define a dedicated refinement region with a finer resolution in these
areas. However, this approach is not suitable for automatic re-meshing of
different device types.
A newer approach is the generation of boundary conforming meshes [130]. In this
approach the boundaries of a certain material segment are the starting
conditions for a mesh generation by offsetting mesh lines from the boundary by
a certain distance, which increases as the mesh lines propagate into the
material segment. This method yields excellent results for resolving critical
channel areas as discussed above. However, it generates unwanted mesh points in
areas which are not related to the active region of devices. Therefore to
suppress this generation, a lot of user interaction has to be performed, do
define the interesting segments in the structure.
A more general and automatic approach is a two step strategy to generate a
suitable device simulation grid. First a coarse grid is used with the
device simulator to obtain a coarse representation of the physical
fields in the device. Based on this solution a physical field is
chosen as the refinement criteria for a second iteration of the
re-meshing process. For a CMOS device an appropriate field would give the
carrier density in the device. One Drawback of this approach is the
possibility of big errors in the initial solution of the physical
fields, which could lead to convergence problems in the second
iteration of the re-meshing. Generally the two step strategy demands more
calculation time. For big two-dimensional grids or three-dimensional
grids this method can, however, lead to much faster device simulations because
of improved convergence. Some problems cannot even be solved with a simple one-step
approach.
Figure 3.8 shows the algorithm of both methods
including the possible re-meshing criterion.
Figure 3.8:
Strategies for re-meshing structures generated by
process simulation. (a) Straight forward single step method (b) Two-step method
(a)
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(b)
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A simple example of the refinement of a process simulation mesh of a CMOS
transistor which has to be simulated for drain to substrate breakdown is shown in
Figure 3.9.
Figure 3.9:
Comparison of automatically and manually refined meshes (a)
Initial coarse grid (b) 1st iteration (c) 2nd iteration (d) manually
refined grid
(a)
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(b)
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(c)
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(d)
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In Figure 3.9(a) a very coarse initial grid
interpolated from the process simulation grid is shown. This grid is used
for a first analysis of the junction breakdown between the drain and the
substrate of the NMOS transistor. The resulting electric field inside the
device extracted when the reverse current between drain an substrate reaches
a certain level is used with gradient refinement criteria for the first
iteration shown in Figure 3.9(b). The results of a device
simulation with this grid are used for a 2nd iteration with the same
criteria. The resulting mesh is shown in Figure 3.9(c). It can be
seen clearly from this figure, that the fine mesh follows the field
distribution in the breakdown situation very smoothly. As a comparison a
mesh which is created by manually placed refinement boxes is shown in
Figure 3.9(d). The electrical characteristics of the reverse biased
drain/substrate diode for these different grids can be seen in
Figure 3.10.
Figure 3.10:
Comparison of the different meshes in terms of device
simulation results
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The initial grid gives a moderately inaccurate result (the simulation was
stopped when the ionization integral inside the structure reached unity to speed
up the simulation). The iterative and the manually optimized meshes give
nearly identical results. However, to set up such a mesh manually human
interaction is necessary, which is not suitable for automatic simulation
flows. Therefore the approach to generate the mesh refinement based on initial
device simulations is the method of choice for a stable automated mesh
generation.
Drawbacks of this method can be an increased mesh node count,
because the refinement is not restricted to certain parts of the
device.
Next: 3.6 Contact Definition
Up: 3. The TCAD Concept
Previous: 3.4 Process Simulation
R. Minixhofer: Integrating Technology Simulation
into the Semiconductor Manufacturing Environment