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List of Figures

1.1 Schematic representation of an IC. The FEOL indicates all those wafer processing steps since the wafer enters production. It includes all the films needed to form transistors, capacitors, resistors and local interconnects. BEOL are all those process steps used for forming global interconnections.
1.2 Interconnect evolution: (a) The 2D interconnect structure (long interchip connections between logic and memory). (b) The SOC configuration (Larger die with issues regarding process, design and time to market). (c) The 3D stacked Si (Shortest interconnects between functions).
1.3 In (a) different discrete devices with their own packages interconnected using a circuit board. (b) The SiP configuration, where multiple dies and/or CSP are all connected on a common substrate.
1.4 (a) Indicates the 2.5D IC architecture and (b) the 3D IC architecture.
1.5 Process steps for Via First, Via Middle, and Via Last. For Via First and Via Middle, the TSV etching proceeds from the top of the wafer, where BEOL devices are located. Only in the Via Last process does the TSV etching initiate from the back of the wafer and the FEOL metals are used as an etch-stop layer
1.6 Simplified TSV fabrication steps. The first processing step is the hole generation through the Si, the second processing step is the TSV isolation line deposition, the third processing step is the building of the TSV barrier layer, and the fourth processing is the metal fill process for filled TSV (bottom) or the metal linear deposition (top). Further steps include wafer thinning and backside processing, not depicted here.
1.7 Channel crack in a thin film lying on top of a substrate. In this example the substrate and the interface are intact.
1.8 Interface crack between two materials. This phenomenon is also known as delamination.
1.9 Ratcheting. The picture on the left indicates the structure before metal deformation. The picture on the right denotes the deformed structure after many thermal cycles.
1.10 Schematic representation of the electromigration phenomenon. The conducting electrons transfer the momentum to the metal ions. This causes the gradual movement of ions and the formation of voids and consequently hillocks in the conductor material.
1.11 Due to a high stress the voids form and can increase in size leading to an open circuit failure.
1.12 Discretized domain and the corresponding elements and nodes.
2.1 Coordinate system. At the reference configuration t = 0 the body B is underformed. The body b is deformed at time t > 0. X1,X2 and X3 refer to the material coordinates at t = 0. x1,x2 and x3 are spatial coordinates at t > 0. u indicates the displacement vector.
2.2 Schematic representation of a body subjected to a force ΔF.
2.3 Stress components on an infinitesimal cube.
2.4 Example of stress-strain curve for a ductile material.
2.5 Polycrystalline material.
2.6 Atom movements in elastic and slip deformation.
2.7 Piecewise linear hat-functions
2.8 An unformed body (left) and a deformed body (right).
3.1 (a) A sample of load displacement curve. (b) An indenter penetrating in to a sample.
3.2 Examples of load-displacement (P-d) curves for different material responses and properties. The pop-in event in (e) indicates cracking or delamination.
3.3 Two-dimensional representation of a TSV structure and an indenter. The dashed line indicates the axis of symmetry. Only a quarter of the system is represented. Al is shown in yellow, W in black, SiO2 in orange, and Si in red. The multilayer consists of different materials. The indenter is spatially external to the TSV (the via height and width of the TSV in the figure do not represent the real size, under consideration).
3.4 Stress-strain curve showing the elastic part before reaching the σys0. At σys0 the plastic deformation begins.
3.5 FEM result, illustrating the displacement (μm) of the indenter inside of the TSV. The displacement peaks at about 3 μm.
3.6 The loading part of the nanoindentation process is plotted and it illustrates a comparison between the FEM simulation and experimental data.
3.7 This image depicts normalized Von Mises stress development in the TSV. Two physical regions with high mechanical stress can be identified. The first is located in the TSV area above the indenter and the second is at the corner of the TSV. This perspective of the structure differs from Figure 3.3 in order to highlight those areas with a high concentration of mechanical stress.
3.8 Normalized Von Mises stress versus displacement into surface.
4.1 The three crack opening modes. (a) indicates mode I (opening), (b) mode II (sliding) and (c) mode III (tearing).
4.2 Coordinate at the crack-tip.
4.3 Tip of a bimaterial crack.
4.4 Example of crack advance in two-dimensional.
4.5 A possible (arbitrary) path around the crack-tip for the J-integral.
4.6 Schematic of the Open TSV geometry under consideration. The open TSV is integrated in the silicon of the wafer. The alternating layers with different thickness are located at the bottom. There are the interfaces where a failure of the device due to delamination is expected.
4.7 Schematic representation of the studied system. In the inset the path Γ for the J integral calculation is shown. The variable a indicates the crack length and w the width of the layer.
4.8 The energy release rate G for different initial stresses (Al) and crack lengths in the interface Ti/Al. Simulation conditions were σTi=-50 MPa, hTi=0.15 μm, and hAl=0.5 μm.
4.9 The energy release rate G for different initial stresses (Ti) and crack lengths in the interface Ti/Al. Simulation conditions were σAl=-100 MPa, hTi=0.15 μm, and hAl=0.5 μm.
4.10 The energy release rate G for different initial stresses (SiO2) and crack lengths in the interface Si/SiO2. Simulation conditions were hSi=5 μm, and hSiO 2=1.4 μm.
4.11 The energy release rate G for different initial stresses (W) and crack lengths in the interface SiO2/W. Simulation conditions were σSiO 2=-100 MPa, hW=0.1 μm and hSiO 2=0.4 μm.
4.12 The energy release rate G for different initial stresses (SiO2) and crack lengths in the interface SiO2/W. Simulation conditions were σW=1.25 GPa, hSiO 2=0.4 μm, and hW=0.1 μm.
4.13 The energy release rate G for different initial stresses (TiN) and crack lengths in the interface SiO2/TiN. Simulation conditions were σSiO 2=-100 MPa, hSiO 2=1 μm, and hTiN=0.15 μm.
4.14 The energy release rate G for different initial stresses (SiO2) and crack lengths in the interface SiO2/TiN. Simulation conditions were σTiN=-50 MPa, hSiO 2=1 μm, and hTiN=0.15 μm.
4.15 The energy release rate G for different thicknesses (W) and crack lengths in the SiO2/W interface. Simulation conditions were σSiO 2=-100 MPa, σW=1.25 GPa, and hSiO 2=0.4 μm.
4.16 The energy release rate G for different thicknesses (SiO2) and crack lengths in the SiO2/W interface. Simulation conditions were σSiO 2=-100 MPa, σW=1.25 GPa, and hW=0.1 μm.
4.17 The energy release rate G for different thicknesses (TiN) and crack lengths in the SiO2/TiN interface. Simulation conditions were σSiO 2=-100 MPa, σTiN=-50 MPa, and hSiO 2=1 μm.
4.18 The energy release rate G for different thicknesses (Al) and crack lengths in the Ti/Al interface. Simulation conditions were σTi=-50 MPa, σAl=-100 MPa, and hTi=0.15 μm.
4.19 The energy release rate G for different thicknesses (SiO2) and crack lengths in the Si/SiO2 interface. Simulation conditions were σSiO 2=-100 MPa and hSi=5 μm.
4.20 The energy release rate G for different force and crack lengths in the SiO2/W interface. Simulation conditions were σSiO 2=-100 MPa, σW=1.25 GPa, hSiO 2=0.4 μm, and hW=0.1 μm.
4.21 The G for different forces and crack lengths in the Si/SiO2 interface. Simulation conditions were σSiO 2=-100 MPa, hSiO 2=1.4 μm, and hSi=5 μm.
4.22 The G for different forces and crack lengths in the SiO2/TiN interface. Simulation conditions were σSiO 2=-100 MPa, σTiN=-100 MPa, hSiO 2=1 μm, and hTi=0.15 μm.
4.23 The G for different forces and crack lengths in the Ti/Al interface. Simulation conditions were σTi=-50 MPa, σAl=-100 MPa, hTi=0.1 μm, and hAl=0.5 μm.
4.24 Schematic representation of the studied system. On the top a force (F) was applied, and at the bottom two fixed points were used as bearings.
4.25 Experimental results for Sample 1 and Sample 2. The gray area indicates the steady state region where delamination appears.
4.26 Experimental results for Sample 3, Sample 4, and Sample 5. The gray area indicates the steady state region where delamination appears.
4.27 FEM simulation of the 4PB test. The legend indicates the Von Mises Stress (106 N/m2). Due to the boundary condition the stress development in the bottom layer can be observed. In the inset a zoomed-in section of the crack, with the mesh used is shown.
4.28 Example of the obtained FEM results compared with the stresses calculated using (4.40). Here σxx as a function of r is shown.
4.29 Example of the obtained FEM results compared with the stresses calculated using (4.40). Here τxy as a function of r is shown.
4.30 G obtained from FEM simulations. Crack length in the range from 1 mm to 10 mm was simulated.
4.31 G obtained from FEM simulations. The crack length in the range from 1 mm to 10 mm was simulated.
4.32 Structure used for a comparison between the two methods.
4.33 G values obtained using the J-Integral method and the linear regression method. Crack lengths in the range from 0.1 mm to 0.9 mm were simulated. The percentage of variation between the two methods is reported.
5.1 Three steps of the V-W growth process. (a) indicates the nucleation of the islands where compressive stress occurs, (b) indicates the coalescence process where the islands impinge upon each other, and (c)-(d) is the thickening process where a homogeneous film is formed. The properties of the deposited material distinguish two kinds of microstructure, Type 1 (for low adatom mobility materials) or Type 2 (for high adatom mobility materials).
5.2 Stress evolution during the deposition process for both kinds of materials.
5.3 (a) A schematic illustration of the DRIE process, where a passivation layer protects the sidewalls during the subsequent etching cycle. (b) Etched trench structure after 8 deposition/etch cycles.
5.4 Half-cylindrical islands which lie on the substrate.
5.5 Schematic diagram of the impingement of the islands is shown. The dashed lines indicate the island before the coalescence process and the solid lines depict the homogeneous film (after the coalescence of the islands).
5.6 hgb,i during film growth.
5.7 Behavior of vgb as a function of thickness for different vg.
5.8 σxx (in GPa) during the initial nucleation of W isolated islands. Development of compressive stress is observable at the W islands.
5.9 Behavior of the compressive stress due to the Laplace pressure for different grain sizes before coalescence. For all the samples Rfr=10 nm was assumed.
5.10 Behavior of the compressive stress for different values of Rfr.
5.11 ⟨σxx⟩ dependence on film thickness for different grain size during V-W growth. After the coalescence, the stress becomes tensile and constant.
5.12 Normalized ⟨σxx⟩×hf for different grain size during growth.
5.13 Distributions of σxx stress (GPa) at the point of coalescence for three different samples are shown.
5.14 Normalized average stress as a function of film thickness measured for the three different samples is shown. As the films thicken, their stress reach a steady value. All the stresses are normalized at the steady value.
5.15 Normalized ⟨σxx⟩ distribution in a scalloped structure (hs=0.1 μm and ws=1 μm) for three different film thicknesses (~0 nm (a), 200 nm (b), and 400 nm (c)).
5.16 Normalized average stress as a function of film thickness measured for different samples. In (a) the height of the scallops was varied, keeping constant the width of 0.75 μm. In (b) the height of 0.1 μm was fixed and the weight of the scallops was varied.
5.17 Normalized average stress as a function of film thickness measured for different samples. In (a) the height of the scallops was varied, keeping constant the width of 1 μm. In (b) the height of 0.2 μm was fixed and the width of the scallops was varied.
5.18 Normalized average stress as a function of film thickness measured for different samples. In (a) the height of the scallops was varied, keeping constant the width of 1.25 μm. In (b) the height of 0.3 μm was fixed and the width of the scallops was varied.
5.19 Schematic representation of grain overtaking. As the film thickness increases the grain which grows between scallops (indicated in red) is overtaken by the neighboring grains.
5.20 The crossed data points are the experimental data from [1, 2], and the lines are the results of the FEM simulations.
5.21 Average stress obtained from FEM simulations for different deposition temperatures.
5.22 The crossed data points are the experimental data from [3] and the lines represent the FEM simulations.
5.23 Average stress measured from FEM simulations for different thicknesses is shown.

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