[1] E. Chason, “A Kinetic Analysis of Residual Stress Evolution in Polycrystalline
Thin Films,”
[2] E. Chason, J. W. Shin, S. J. Hearne, and L. B. Freund, “Kinetic Model
for Dependence of Thin Film Stress on Growth Rate, Temperature, and
Microstructure,”
[3] E. Chason, A. Engwall, F. Pei, M. Lafouresse, U. Bertocci, G. Stafford, J. A.
Murphy, C. Lenihan, and D. N. Buckley, “Understanding Residual Stress in
Electrodeposited Cu Thin Films,”
[4] C. Lécuyer, D. C. Brock, and J. Last,
[5] J. S. Kilby, “Invention of the Integrated Circuit,”
[6] R. R. Schaller, “Moore’s Law: Past, Present and Future,”
[7] A. N. Saxena,
[8] E. M. Moore, “Cramming More Components Onto Integrated Circuits,”
[9] G. E. Moore, “Progress in Digital Integrated Electronics,” in
[10] M. Dalmau,
[11] J. D. Meindl, “Ultra-Large Scale Integration,”
[12] G. Bose, “IC Fabrication Technology,” 2014.
[13] K. Reinhardt and W. Kern,
[14] P. Garrou, C. Bower, and P. Ramm,
[15] R. H. Bruce, W. P. Meuli, and J. Ho, “Multi Chip Modules,” in
[16] R. S. Patti, “Three-Dimensional Integrated Circuits and the Future of
System-on-Chip Designs,”
[17] K. L. Tai, “System-in-Package (SIP): Challenges and Opportunities,” in
[18] A. Papanikolaou, D. Soudris, and R. Radojcic,
[19] S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan, and F. Carson, “3d
TSV Processes and its Assembly/Packaging Technology,” in
[20] P. Ramm, J. J. Q. Lu, and M. M. V. Taklo,
[21] W. Arden, M. Brillouët, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf,
“More than-Moore white paper,”
[22] J. Burghartz,
[23] M. Puech, J. M. Thevenoud, J. M. Gruffat, N. Launay, N. Arnal, and
P. Godinat, “Fabrication of 3D Packaging TSV using DRIE,” in
[24] F. Laermer and A. Schilp, “Method of Anisotropically Etching Silicon,” 1996.
[25] K. H. Lu, X. Zhang, S. K. Ryu, J. Im, R. Huang, and P. S. Ho,
“Thermo-Mechanical Reliability of 3-D ICs Containing Through Silicon Vias,”
in
[26] I. D. Wolf, K. Croes, O. V. Pedreira, R. Labie, A. Redolfi, M. V. D. Peer,
K. Vanstreels, C. Okoro, B. Vandevelde, and E. Beyne, “Cu Pumping in TSVs:
Effect of Pre-CMP Thermal Budget,”
[27] M. J. Wolf, B. Dretschkow, T.and Wunderle, N. Jurgensen, G. Engelmann,
O. Ehrmann, A. Uhlig, B. Michel, and H. Reichl, “High Aspect Ratio TSV Copper
Filling with Different Seed Layers,” in
[28] D. Malta, E. Vick, S. Goodwin, C. Gregory, M. Lueck, A. Huffman, and
D. Temple, “Fabrication of TSV-Based Silicon Interposers,” in
[29] J. Kraft, F. Schrank, J. Teva, J. Siegert, G. Koppitsch,
C. Cassidy, E. Wachmann, F. Altmann, S. Brand, C. Schmidt, and M. Petzold,
“3D Sensor Application with Open Through Silicon Via Technology,” in
[30] K. Kondo, M. Kada, and K. Takahashi,
[31] Toshiba,
[32] J. Liu, O. Salmela, J. Sarkka, J. Morris, P. E. Tegehall, and C. Andersson,
[33] Z. Suo, “Reliability of Interconnect Structures,”
[34] Y. M. Desai,
[35] J. Betten,
[36] A. F. Bower,
[37] D. Gross and T. Seelig,
[38] A. C. Fischer-Cripps,
[39] G. Q. Zhang, W. D. van Driel, and X. J. Fan,
[40] J. Schröder
and K. Hackl,
[41] D. Hull and D. J. Bacon,
[42] L. B. Freund and S. Suresh,
[43] D. Rees,
[44] A. R. A. Ragab and S. E. A. Bayoumi,
[45] J. W. Hutchinson, “Stresses and Failure Modes in Thin Films and Multilayers,”
[46] A. Oechsner and
M. Merkel,
[47] J. N. Reddy,
[48] M. Kaltenbacher,
[49] O. C. Zienkiewicz, R. L. Taylor, and J. Z. Zhu,
[50] G. R. Liu and S. S. Quek,
[51] B. Swinnen, W. Ruythooren, P. D. Moor, L. Bogaerts, L. Carbonell, K. D.
Munck, B. Eyckens, S. Stoukatch, D. S. Tezcan, Z. Tokei, J. Vaes, J. V. Aelst,
and E. Beyne, “3D Integration by Cu-Cu Thermo-Compression Bonding of
Extremely Thinned Bulk-Si Die Containing 10
[52] S. Hashmi,
[53] V. Cherman, G. V. der Plas, J. D. Vos, A. Ivankovic, M. Lofrano, V. Simons,
M. Gonzalez, K. Vanstreels, T. Wang, R. Daily, W. Guo, G. Beyer, A. L. Manna,
I. D. Wolf, and E. Beyne, “3D Stacking Induced Mechanical Stress Effects,” in
[54] C. Ko and K. Chen, “Wafer-Level Bonding/Stacking Technology for 3D
Integration,”
[55] X. Li and B. Bhushan, “A Review of Nanoindentation Continuous Stiffness
Measurement Technique and its Applications,”
[56] N. K. Mukhopadhyay and P. Paufler, “Micro- and Nanoindentation Techniques
for Mechanical Characterisation of Materials,”
[57] H. Hertz, “On the Contact of Elastic Solids,”
[58] D. Tabor,
[59] A. P. Karmarkar, X. Xiaopeng, and V. Moroz, “Performanace and Reliability
Analysis of 3D-Integration Structures Employing Through Silicon Via (TSV),” in
[60] L. Hofmann, S. Dempwolf, D. Reuter, R. Ecke, K. Gottfried, S. Schulz,
R. Knechtel, and T. Geßner, “3D Integration Approaches for MEMS and CMOS
Sensors Based on a Cu Through-Silicon-Via Technology and Wafer Level Bonding,”
in
[61] O. Tabata, T. Tsuchiya, O. Brand, G. K. Fedder, C. Hierold, and J. G.
Korvink,
[62] COMSOL, “COMSOL Multiphysics
[63] J. Lubliner,
[64] H. D. Espinosa, B. C. Prorok, and M. Fischer, “A Methodology for Determining
Mechanical Properties of Freestanding Thin Films and MEMS Materials,”
[65] H. D. Espinosa, B. C. Prorok, and B. Peng, “Plasticity Size Effects in
Free-Standing Submicron Polycrystalline FCC Films Subjected to Pure Tension,”
[66] H. Pelletier, J. Krier, A. Cornet, and P. Mille, “Limits of Using Bilinear
Stress–Strain Curve for Finite Element Modeling of Nanoindentation Response on
Bulk Materials,”
[67] L. Filipovic, A. P. Singulani, F. Roger, S. Carniello, and S. Selberherr,
“Intrinsic Stress Analysis of Tungsten-Lined Open TSVs,”
[68] M. Kuna,
[69] A. A. Griffith, “The Phenomena of Rupture and Flow in Solids,”
[70] C. T. Sun and Z. Jin,
[71] R. P. Wei,
[72] E. Zeidler,
[73] B. M. Malyshev and R. L. Salganik, “The Strength of Adhesive Joints Using the
Theory of Cracks,”
[74] J. R. Rice, “A Path Independent Integral and the Approximate Analysis of
Strain Concentration by Notches and Cracks,”
[75] B. Budiansky and J. R. Rice, “Conservation Laws and Energy-Release Rates,”
[76] R. E. Smelser and M. E. Gurtin, “On the J-Integral for Bi-Material Bodies,”
[77] R. H. Myers, D. C. Montgomery, G. G. Vining, and T. J. Robinson,
[78] R. A. Naik and J. Crews, J. H., “Determination of Stress Intensity Factors
for Interface Cracks Under Mixed-Mode Loading,”
[79] K. H. Lu, S.-K. Ryu, Q. Zhao, X. Zhang, J. Im, R. Huang, and P. S.
Ho, “Thermal Stress Induced Delamination of Through Silicon Vias in 3-D
Interconnects,” in
[80] F. Roger, J. Kraft, K. Molnar, and R. Minixhofer, “TCAD Electrical
Parameters Extraction on Through Silicon Via (TSV) Structures in a 0.35
[81] L. Filipovic and S. Selberherr, “The Effects of Etching and Deposition on the
Performance and Stress Evolution of Open Through Silicon Vias,”
[82] A. A. Volinsky, N. R. Moody, and W. W. Gerberich, “Interfacial Toughness
Measurements for Thin Films on Substrates,”
[83] P. J. Wei, W. L. Liang, C. F. Ai, and J. F. Lin, “A New Method for
Determining the Strain Energy Release Rate of an Interface Via Force–Depth Data
of Nanoindentation Tests,”
[84] M. S. Kennedy, D. F. Bahr, and N. R. Moody, “The Effect of Nonuniform
Chemistry on Interfacial Fracture Toughness,”
[85] M. J. Cordill, D. F. Bahr, N. R. Moody, and W. W. Gerberich, “Recent
Developments in Thin Film Adhesion Measurement,”
[86] C. Krauss, S. Labat, S. Escoubas, O. Thomas, S. Carniello, J. Teva, and
F. Schrank, “Stress Measurements in Tungsten Coated Through Silicon Vias for 3D
Integration,”
[87] P. G. Charalambides, J. Lund, A. G. Evans, and R. M. McMeeking, “A Test
Specimen for Determing the Fracture Resistance of Bimaterial Iinterfaces,”
[88] I. Hofinger, M. Oechsner, H.-A. Bahr, and M. V. Swain, “Modified Four-Point
Bending Specimen for Determining the Interface Fracture Energy for Thin, Brittle
Layers,”
[89] R. C. Cammarata, T. M. Trimble, and D. J. Srolovitz, “Surface Stress Model
for Intrinsic Stresses in Thin Films,”
[90] S. C. Seel,
[91] E. Chason, B. W. Sheldon, L. B. Freund, J. A. Floro, and S. J. Hearne,
“Origin of Compressive Residual Stress in Polycrystalline Thin Films,”
[92] R. Koch, “The Intrinsic Stress of Polycrystalline and Epitaxial Thin Metal
Films,”
[93] I. Committee
[94] N. Ranganathan, D. Y. Lee, L. Youhe, G. Q. Lo, K. Prasad, and K. L. Pey,
“Influence of Bosch Etch Process on Electrical Isolation of TSV Structures,”
[95] L. Filipovic, R. L. de Orio, and S. Selberherr, “Process and Reliability of
SF
[96] J. A. Floro, E. Chason, R. C. Cammarata, and D. J. Srolovitz, “Physical
Origins of Intrinsic Stresses in Volmer
[97] F. Roger, A. Singulani, S. Carniello, L. Filipovic, and S. Selberherr, “Global
Statistical Methodology for the Analysis of Equipment Parameter Effects on TSV
Formation,” in
[98] J. A. Floro and E. Chason, “Curvature Based Techniques for Realtime Stress
Measurements During Thin Film Growth,”
[99] R. C. Cammarata, “Surface and Interface Stress Effects in Thin Films,”
[100] W. D. Nix and B. M. Clemens, “Crystallite Coalescence: A Mechanism for
Intrinsic Tensile Stresses in Thin Films,”
[101] L. B. Freund and E. Chason, “Model for Stress Generated Upon Contact of
Neighboring Islands on the Surface of a Substrate,”
[102] L. Vitos, A. V. Ruban, H. L. Skriver, and J. Kollár, “The Surface Energy of
Metals,”
[103] F. Spaepen, “Interfaces and Stresses in Thin Films,”
[104] C. Friesen, S. C. Seel, and C. V. Thompson, “Reversible Stress Changes at All
Stages of Volmer–Weber Film Growth,”
[105] R. Koch, D. Hu, and A. K. Das, “Compressive Stress in Polycrystalline
Volmer-Weber Films,”
[106] A. Rajamani, B. W. Sheldon, E. Chason, and A. F. Bower, “Intrinsic Tensile
Stress and Grain Boundary Formation During Volmer-Weber Film Growth,”
[107] S. Sivaram,