1.2 Summary of Previous Works

New structures such as dual-gate oxide devices [26,27], buried gate oxide devices [28], lateral U-diode MOSFETs (LUDMOSFETs) [29,16], super-junction (SJ) devices [30,31,32,33], trench lateral power MOSFETs with a trench bottom source contact (TLPM/S) [34], multi-channel devices [35], lateral trench gate [36], and folded gate LDMOS transistors (FG-LDMOSTs) [37] have been proposed to improve the performance of conventional power devices.

LUDMOSFETs are based on the concept of a trench diode (or U-diode). The trench of the LUDMOSFETs reduces the potential crowding under the gate edge, allowing a higher BV with reduced drift length. Super-junction devices such as COOLMOS [31] and MDmesh [32] assume complete charge balance in the drift region. This results in a significant reduction of $R_\mathrm{sp}$. TLPM/S have a trench bottom source contact. The polysilicon source is connected to the silicon substrate at the bottom of the trench and the channel is created on the side wall at the gate area. Because of the reduced cell pitch, it allows to increase the channel area. Multi-channel devices have several separated gates which are connected together. This approach leads to an improvement in the on-state performance of the device. FG-LDMOSTs have been suggested to increase the channel area without consuming more chip area. These can be made by trenching the silicon surface before the gate formation, and the channel resistance is reduced by the increased channel area.

The conventional LDMOSFET has the channel region on the surface. The channel is obtained by a double diffusion process. A lateral trench gate LDMOSFET uses narrow trenches as channels. Contrary to the conventional vertical trench MOSFETs with current flow in vertical direction, the lateral trench gate is formed laterally on the side wall of a trench and the channel current flows in lateral direction through the trench side walls. This gives an increased channel area compared to that of conventional LDMOSFETs.

One of the key issues in the realization of such `smart power' technology is the isolation of power devices and low-voltage circuitry. In junction isolation (JI) the devices are electrically isolated from each other by reverse biased $pn$-junctions. This technology uses bulk silicon as a starting material. It has been the dominant process in industry.

SOI technology constitutes an attractive alternative to the traditional junction isolation. Advantages of SOI technology are the superior isolation, reduced parasitic capacitances and leakage currents, and the superior high temperature performance compared to the traditional JI [7,38,39,40]. The isolation area of a JI becomes larger as the voltage rating of the device is increased. In the case of SOI devices it depends only on the fabrication process, which results in a compact chip size of high-voltage devices. These advantages allow monolithic integration of multiple power devices and low-voltage control circuitry on the same chip. When high-voltage devices over 100V are integrated on an SOI wafer, the isolation area between devices shrinks and lower leakage currents result in greatly improved high temperature performance. SOI-LDMOSFETs are increasingly used as output power devices in smart power applications. However, the operation of SOI power devices is limited by self-heating effects during switching and some fault conditions such as short-circuit. When a short-circuit occurs in the drain (ex. SOI-LDMOSFET) path, the current starts to increase until it reaches its maximum value, which defined by the supply voltage and gate voltage. When the self-heating due to this large amount of current reaches a critical point, thermal instability ensues. This thermal instability can occur at relatively low values of gate voltage and can give a thermal safe operating area (SOA) that is within the electrical SOA [41]. The electrical SOA is reduced further by the temperature increase of the device. Since the buried oxide underneath the device is a good thermal insulator, the temperature rise inside SOI power devices can be much higher than that of bulk silicon devices. To solve this problem, partial-SOI (P-SOI) technology was suggested [42,43], where a silicon window helps to reduce self-heating.