5.2.1 Analyzed Transistor

In this example, an NMOS device with $0.25 \ {\rm\mu m}$ geometry gate length and $5 \ {\rm nm}$ gate oxide thickness is optimized. The supply voltage for this device is $1.5 \ {\rm V}$. The analytical doping profile consists of a retrograde well and a channel implant, both generated with Gauß functions (see Appendix B.5). Control parameters are the depth, the deviation, and the doping level of the channel implant. As the doping levels are varying in a large range, a logarithmic transformation is used.

The optimization target is defined to a achieve maximum on-current. Without a constraint, this optimization would result in a decrease of the threshold voltage only. The off-current would be drastically increased because of its exponential dependence on threshold voltage in the sub-threshold region [60]. A large off-current leads to high system standby power which does not meet the requirements for present and future MOSFET technology [64]. Therefore, the off-current is entered as a constraint for the optimization process and kept below a constant value. Two device simulation steps have to be performed to extract the two current-values. To increase the speed of the optimization, these two steps are done in parallel.

A uniformly doped device is used as the initial device, the on-current is improved drastically by the presented optimization process. Together with the flexible framework features, tasks like reverse engineering of doping profiles can be realized.