8 Design rules for PCBs inside a metallic enclosure with apertures

PCB EMC rules are commonly used to obtain a PCB layout with sufficiently good EMC properties to achieve EMC compliance of a device. Design guidelines for PCB layout are described by [111], [112], [113], [114], and [115]. The four most important PCB design rules are [111]:

• Minimize the loop areas associated with high-frequency power and signal currents.
• Do not split, gap, or cut the signal return plane.
  • A nearby current return path has to be provided for transient signal traces.
• Do not locate high-speed circuitry between connectors.
• Control signal transition times.
  • Use a logic family which is only as fast as the application requires.
  • Put a resistor or a ferrite in series with a device's output.

Additional rules depend on the application and on the enclosure of the device. The EMC performance of a device with a metallic enclosure and a PCB inside depends on the coupling of the sources on the PCB to the field at the apertures of the enclosure. The aperture field causes direct radiation and coupling to cables which are leaving the enclosure. Feed through filters are a solution to reduce the EMI from these cables. However, this is too costly for devices with multiple pin connectors, such as, for example, boards with backplane connectors or automotive control devices as depicted in Figure 1.1(a). The field coupling from traces and components on the PCB to the enclosure apertures is not only relevant for the electromagnetic emission from a device. The coupling from internal sources to the external field is the same as the coupling from external sources to the internal field, according to the reciprocal principle [102]. Therefore, the coupling is also relevant for the susceptibility of a device. This chapter investigates the quantitative differences of the radiated power from the slot of a slim rectangular enclosure between different trace connection routings and source placements on the PCB. Traces are modeled with 0.2mm width and 0.65mm height above the ground plane. They are driven with a 10mV source voltage with a source impedance equal to the characteristic impedance of the trace $Z_w$. This simulates an IC driver output with correct series termination. At the load position traces are terminated with a 10pF capacitance, simulating the input capacitance of typical IC inputs. Although the values will vary for real devices and other trace geometries, the comparison provides a reasonable quantitative insight for practically situations. For single sources a source current of 10$\mu$A is used in the calculations. One may weight the diagram values with the actual harmonic magnitude values of signals in a dedicated application to obtain quantitative first order predesign information about the EMC performance of a device. The design rules in Section 5.8 and in Section 7.1.3 are validated to provide quantitative information about their relevance on the design. Especially the rules regarding the trace routing close to metallic enclosure walls can be generalized to arbitrary enclosure shapes. Finally, this chapter presents a table with a summary of the extracted rules with quantitative information.

Subsections

• 8.1 Rule 1: Trace placement symmetric to the enclosure symmetry reduces the coupling up to the second enclosure resonance
• 8.2 Rule 2: Trace placement parallel and close to metallic enclosure walls reduces EMI, trace placement orthogonal and close to enclosure walls increases EMI
• 8.3 Rule 3: Trace placement in the middle of the enclosure slot reduces the EMI at the first resonance
• 8.4 Rule 4: Reduction of the trace height d above the ground plane reduces EMI
• 8.5 Rule 5: Single source placement closer to an enclosure wall reduces EMI
• 8.6 Rule 6: Shielding reduces the common mode coupling
• 8.7 Rule 7: A ground plane under an IC reduces EMI
• 8.8 Summary of the design guidelines

C. Poschalko: The Simulation of Emission from Printed Circuit Boards under a Metallic Cover