8.8 Summary of the design guidelines

• Rule 1: Trace placement symmetric to the enclosure symmetry reduces the coupling up to the second enclosure resonance
  • The trace source and load positions are symmetric to the enclosure symmetry.
  • The guideline must be considered at component placement on the PCB.
  • The load dependent emission reduction is greater than 20dB compared to a trace, parallel to the enclosure symmetry line. Example in Figure 8.1.
• Rule 2: Trace placement parallel and close to metallic enclosure walls reduces EMI, trace placement orthogonal and close to enclosure walls increases EMI
  • The guideline must be considered at component placement on the PCB.
  • The load dependent emission reduction is greater than 20dB compared to a trace, normal to the enclosure wall. Example in Figure 8.2.
  • Emission reduction from the closer placement is about 10dB (Figure 8.3).
  • Emission reduction from the parallel orientation is about 10dB (Figure 8.3).
• Rule 3: Trace placement in the middle of the enclosure slot reduces the EMI at the first resonance
  • The guideline must be considered at component placement on the PCB.
  • The load dependent emission reduction is typically greater than 20dB compared with a different trace placement. Example in Figure 8.6.
  • The emission below the first resonance is higher.
• Rule 4: Reduction of the trace height d above the ground plane reduces EMI
  • Realizable with thin dielectric layers on the PCB and thin IC packages.
  • A trace width reduction must be carried out, when the dielectric layer thickness of the PCB is changed to conserve the characteristic impedance of the traces.
  • Check the power distribution impedances and transfer parameters.
  • Broad band EMI reduction estimation: R₂₁=20log(d₂/d₁)
• Rule 5: Single source placement closer to an enclosure wall reduces EMI
  • The guideline must be considered at component placement on the PCB.
  • A first order estimation of the emission reduction that is correct close to the wall gives R₂₁=20log(a₂/a₁), where a₁ is the initial distance from the source to the wall and a₂ is the new, reduced distance.
• Rule 6: Shielding reduces the common mode coupling
  • EMI reduction for coplanar shielding: R_{s_21}=20log|(I_trace-I_shield)/I_trace|.
  • PCB shielding cannot reduce the coupling from the vertical interconnects to ICs.
  • Coplanar shielding is efficient for narrow traces, high above the ground plane.
• Rule 7: A ground plane under an IC reduces EMI
  • EMI reduction according to the obtained d/h reduction Þ Rule 4.
  • Vias must connect this ground with the global PCB ground plane, at least close
    to fast signal IC pads.

C. Poschalko: The Simulation of Emission from Printed Circuit Boards under a Metallic Cover