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Since the gate-delay time is proportional to the parasitic capacitance and
inversely proportional to the on-current (5.1), there is an optimal value
for the gate-source spacer length,
, which minimizes the
gate-delay time. The optimal value for the gate-source spacer length is achieved if
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(5.6) |
The optimal gate-source spacer length for a device with zero barrier height for
electrons is
for
and
. For devices
with positive barrier heights the optimal value of the gate-source spacer
length is smaller than that of a device with zero barrier height due to the
higher sensitivity of the on-current with respect to the gate-source spacer
length.
Note that the optimal value for
depends on
. For small values of
the gate-drain parasitic
capacitance dominates the gate-source parasitic capacitance. Therefore, any
further decrease of the gate-source spacer length does not improve the gate-delay
time. As shown in Fig. 5.16, the optimal value of the gate-source spacer
length for the given material and geometrical parameters results in optimized
device characteristics.