5.2.2 Gate-Drain Spacer Length

The transfer characteristics for a device with zero barrier height for electrons is shown in Fig. 5.11-a. In the off-regime the drain current starts to increase due to ambipolar conduction. By further increasing the drain bias this phenomenon becomes more apparent (see Section 5.1.1). Fig. 5.11-b shows that if the drain voltage becomes higher than the gate voltage, the thickness of the drain-sided metal-CNT barrier for holes is reduced. As a result, the parasitic band-to-band tunneling current of holes increases. By increasing the gate-drain spacer length, the band edge profile near the drain contact is less affected by the gate voltage. Therefore, the barrier for holes at the drain-side is thicker and the parasitic tunneling current of holes is suppressed. Fig. 5.11-a shows that, the off-current decreases considerably, as the gate-drain spacer length increases, while the on-current is only weakly affected.

Fig. 5.12 compares the increase of the $\ensuremath{I_\mathrm{on}}/\ensuremath{I_\mathrm{off}}$ ratio as a function of the gate-drain spacer length. In a device with negative barrier height more improvement is achieved. A smaller barrier height for electrons results in a larger barrier height for holes. A negative barrier height for electrons gives a positive barrier height for holes, implying that the tunneling process contributes predominantly the hole current. As a result, for a device with negative barrier height for electrons the parasitic hole tunneling current can be more effectively suppressed than for other device types.

Figure 5.11: a) Transfer characteristics at different drain biases. The increase of the off-current is due to parasitic hole injection at the drain contact. By increasing the gate-drain spacer length ( $L_\textrm {GD}$) the parasitic current of holes at the drain contact decreases. b) Comparison of the band-edge profile for devices with $L_\textrm {GD}$=4 nm and $L_\textrm {GD}$=20 nm. $V_\textrm {G}$= 0.6 V and $V_\textrm {D}$= 0.8 V. As $L_\textrm {GD}$ increases, the band-bending near the drain contact decreases, and the drain-sided metal-CNT barrier is thicker.

Figure 5.12: The ratio of the $I_\textrm {on}$/ $I_\textrm {off}$ versus the gate-drain spacer length ( $L_\textrm {GD}$) for devices with different barrier heights for electrons. Increasing the gate-drain spacer length improves the $I_\textrm {on}$/ $I_\textrm {off}$ ratio for all devices. The device with negative barrier height shows the largest improvement. As the barrier height for electrons decreases, the barrier height for holes increases. Therefore, in a device with negative barrier height for electrons the barrier height for holes is positive. In this case the hole current is more sensitive to the variation of the gate-drain spacer length than it is for other device types. For all results $V_\textrm {D}$=0.6 V was assumed.

Fig. 5.13 compares the effect of the gate-drain spacer length on the output characteristics for devices with different barrier heights. In the device with positive barrier height for electrons, the current at low drain biases decreases as the gate-drain spacer length increases. This behavior can well be understood by considering Fig. 5.10-c. In a device with positive barrier height, electrons in the channel face a barrier at the drain-sided metal-CNT interface. Similar to what we discussed for the gate-source spacer length, with increasing gate-drain spacer length the thickness of the drain-sided metal-CNT barrier increases, such that the drain current will be reduced. If the drain voltage becomes higher than the gate voltage, most of the electrons can reach the drain contact by thermionic emission. In devices with negative and zero barrier height this problem is less apparent, since even at low drain voltages a drain sided-barrier does not form, see Fig. 5.10-a and Fig. 5.10-b.

It should be noticed that, as opposed to conventional MOSFETs, increasing the length of the un-gated area determined by the gate-drain spacer does not increase the channel resistance. In conventional MOSFETs the resistivity of the channel is modulated, when the gate voltage attracts or repels carriers from the channel. For an enhancement-type device the resistance of the un-gated region is high. In contrast, the intrinsic conductance of CNTs is independent from the gate voltage. In conventional MOSFETs carrier transport is diffusive, while in CNT based transistors carrier transport is nearly ballistic. To make a fair comparison with conventional MOSFETs, the effect of the gate-drain spacer length on the output characteristics is investigated for both the ballistic and diffusive transport limit. To study diffusive transport in CNT based transistors an artificially large value for the electron-phonon coupling strength and a small value for the phonon energy is chosen (see Section 5.5.3). Fig. 5.13 shows that even in the case of diffusive transport the length of the un-gated region has a negligible effect on the on-current.

Figure 5.13: The effect of the gate-drain spacer length ( $L_\textrm {GD}$) on the output characteristics for a device with a) negative, b) zero, and c) positive barrier height for electrons. In all cases the results are shown for both ballistic and diffusive transport. For diffusive transport the parameters D=$10^{-1}$ eV$^2$ and $\hbar \omega$=25 meV were used.

M. Pourfath: Numerical Study of Quantum Transport in Carbon Nanotube-Based Transistors