Both tunneling and thermionic emission contribute to the current. The thermionic emission current is controlled by the barrier height and is independent of the barrier width. On the other hand, the tunneling current decreases exponentially with the barrier width. Fig. 5.8 shows that by increasing the gate-source spacer length the width of the SCHOTTKY barrier at the source-sided metal-CNT interface is increased. As a result, the current is reduced.
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Figure 5.9 shows the relative variation of the on-current versus the gate-source spacer length for devices with negative, zero, and positive barrier height for electrons, assuming ballistic transport. The results indicate that scaling of the gate-source space length affects the on-current of devices with positive barrier height more effectively.
Figure 5.10 shows the current density spectrum for devices with negative, zero, and positive barrier height for electrons, assuming ballistic transport. Electrons with energies lower than the barrier height have to tunnel through the source-sided metal-CNT interface barrier to reach the channel, whereas electrons with higher energies are injected by thermionic emission. The relative contributions of thermionic and tunneling strongly depend on the barrier height and the bias point. As shown in Fig. 5.10, at high gate bias even for devices with zero or negative barrier height the tunneling current contributes considerably to the total current. However, in a device with negative barrier height the tunneling current has a smaller contribution to the total current as compared to devices with non-negative barrier height. Therefore, the current is less sensitive to the variation of the gate-source spacer length (Fig. 5.9).
In conclusion, the on-current of all device types decreases as the gate-source spacer length increases. The reduction of the on-current strongly depends on the relative contribution of the tunneling current. To improve the static response it is more appropriate to reduce the gate-source spacer length. However, the reduction of this spacer results in an increase of the gate-source parasitic capacitances which can severely affect the dynamic response of the device. For optimal performance the length of this spacer has to be carefully selected, see Section 5.3.
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