The N+ buried layer is typically the first doping related process step in BiCMOS technology and, hence, the thermal budget associated with this process does not affect the later fabricated CMOS devices. Generally, arsenic or antimony can be chosen for the N+ buried layer implantation. Antimony has the advantage of exhibiting less autodoping during epitaxy and the following heat cycles, but has a lower solubility limit compared to arsenic, which necessitate higher anneal temperatures to activate the antimony.
Vertical and lateral autodoping effects must be considered for N-well and
P-well regions during the epitaxial growth of the EPI-layer to achieve
shallow well profiles ( 
). Otherwise excessive counterdoping has
to be performed [Bor88]. The redistribution of the boron P+ buried
layer doping can be controlled by the epitaxy process temperature.
An accurate approach is required for the isolation technique of the active
device regions, since standard LOCOS technology encroaches to much active
area. It is also of vital importance to keep the thermal budget as low as
possible for BiCMOS technology to preserve the buried layer dopings. To
limit the active area encroachment a poly buffered locos (PBL)
technique is suitable. The polysilicon serves as additional stress relief
layer and allows the usage of thicker nitride layers, which reduce
encroachment [Chi82]. The PBL technology can still be used for 
BiCMOS technology [Ekl89], but moving towards smaller feature sizes
requires trench isolation [Kir91]. An oxide-isolated polysilicon filled
trench penetrates the N+ buried layers between the PMOS and NPN device to
minimize sidewall capacitance and to prevent latchup.
A compromise is required for the design of the wells in BiCMOS technology to include the bipolar device requirements (cf.Section 5.2). Compared to conventional CMOS technology N-well and P-well exhibit a steeper gradient for the above presented twin-well fabrication process. This leads to a higher collector series resistance. However, a deep N+ diffusion is typically used to provide a low resistance path to the N+ buried layer. For the CMOS devices sufficient N-well doping at the field oxide-silicon interface is required to provide adequately field oxide threshold voltages for the PMOS transistor. Generally, several approaches for the BiCMOS well design can be found in literature [Ike87] [Rov90] [Kir91] [Hay94] .
The single-polysilicon non-self-aligned bipolar transistor presented above can be changed into a double-polysilicon emitter-base self-aligned NPN transistor with considerable small increase in process technology [Hay93]. This change results in a smaller base resistance, a lower base-collector capacitance and a higher cut-off frequency.