5.2 BiCMOS Process Technology

  BiCMOS technology is a combination of Bipolar and CMOS technology. CMOS technology offers less power dissipation, smaller noise margins, and higher packing density. Bipolar technology, on the other hand, ensures high switching and I/O speed and good noise performance. It follows that BiCMOS technology accomplishes both - improved speed over CMOS and lower power dissipation than bipolar technology. The main drawback of BiCMOS technology is the higher costs due to the added process complexity. Impurity profiles have to be optimized to both NPN and CMOS issues. This greater process complexity results in a cost increase compared to conventional CMOS technology [Alv93].

The primary approach to realize high performance BiCMOS devices is the addition of bipolar process steps to a baseline CMOS process. We discuss in this section a BiCMOS process flow, emphasizing reliability, process simplicity and compatibility with a CMOS technology. The process recipe is based on the process flow presented by [Alv93].

The integration of the bipolar process steps into the baseline CMOS process flow is given by Table 5.2-1. First, the P+ substrate is replaced by a P- substrate material to incorporate the NPN device into the N-well of the PMOS device. This lower doped substrate increases the susceptibility for latchup. To improve latchup immunity retrograde N-well doping is used. The retrograde doping can be either achieved by high energy ion implantation or by using buried layers. With the first approach no epitaxial layer is required, but ion implantation damage has to be considered. By using buried layers a relatively thick and expensive epitaxial layer has to be grown on top of the substrate. This epitaxial layer hosts the collector of the NPN as well as the P-well and the N-well of the CMOS devices. The epitaxial deposition process must be optimized to reduce material defects and minimize autodoping.

 

CMOS Changes for Bipolar

P+ Substrate P- Substrate Buried N+/P-Layer

P- EPI intrinsic doped EPI-Layer N-Well / P-Well

Well drive-in reduced drive time

Poly Buffer Locos high pressure Oxidation Deep Collector/N+ Resistor Base/P Resistor

Poly Deposition/Doping Poly Deposition Emitter Pattern/Etch Implant Poly Emitter Pattern/Etch Poly LDD Pattern/Implant SWO Deposition/Etch Pattern/Implant N+/P+ S/D

Anneal S/D Anneal optimized for Emitter

 

Due to the usage of the buried layers the well drive-in has to be optimized for bipolar collector requirements. From the bipolar point of view the collector profile should consist of a thin heavily doped collector region (buried N+ layer) and a thick lightly doped collector region on top. The first one minimizes the Kirk effect, where the second one ensures higher collector-base breakdown voltage. The CMOS device on the other hand requires a sufficiently high concentration below the surface to avoid punchtrough, especially as device dimensions are shrinking. Practically, the various conflicting requirements have to be balanced.

This leads to steeper collector N-well profiles which cause an increase of the collector series resistance. To improve the collector series resistance a deep subcollector N+ diffusion is used.

Finally, the same polysilicon material is used for the fabrication of the NMOS and PMOS gates as well as for the bipolar polysilicon emitter. The doping for the emitter junction is usually provided by a N-type implant into the polysilicon, which forms the emitter-base contact during the source-drain anneal of the CMOS device by outdiffusion. The N-type polysilicon gates result in a surface channel NMOS device and a buried channel PMOS device.

• 5.2.1 BiCMOS Process Flow
• 5.2.2 Process Discussion
• 5.2.3 Simulation Results