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4.2.1 Interconnect Example

The formation of a two metal level interconnect structure including aerial image simulation will now be shown. The example given in Fig. 4.6 was simulated using a selected region from the layout of a digital 3 to 8 decoder. Within the scope of layout inclusion for topography simulation the example demonstrates new possibilities for the topography simulation by the extension of the combined layout/solid modeling approach to the inclusion of lithographic aerial image simulation. The detailed analysis of the impact of the aerial image simulation on the capacitance extraction is given in [41].

Figure 4.6: Three-dimensional model of an interconnect structure.

The simulation of the aerial image was performed with the lithography tools from [31]. In the same way as file format conversions and the selection of an area of interest, the aerial image calculation can be started directly from the user interface of PED and results in a continuous intensity distribution at the wafer surface. When a threshold value is applied to this distribution, the intensity can be transformed back into a binary mask. Optionally, the aerial image can be checked for printability of the mask. For the purpose of solid modeling, the binary masks are applied in the same way as shown above for the masks directly specified in the layout. The only difference is, that the binary masks formed by threshold comparison have lost their strictly rectangular shape with well defined sharp corners and straight lines, and exhibit rounded corners and bloated elbow structures as well as shortened or narrow lines.

Figure 4.7: Isolated line of the interconnect structure from Fig. 4.6.

Fig. 4.7 shows how an isolated line from Fig. 4.6 is used for a consequent resistive characterization. The electrical simulation revealed that the current density in some regions is two times larger as compared to simulations, where a proper lithography is not taken into account and interconnect structures are handled as block structures. The resulting voltage drop along the line shown in Fig. 4.7 is also higher than in the case when the line is considered rectangular. When the voltage drop falls out of the range of the device specification, this might require a modification of the layout.

This interconnect example concludes the considerations about geometry generation and solid modeling. Summarizing, the presented approach proves a great flexibility for selecting different strategies for different purposes. With the common file format, some part of the geometry can be defined with accurate topography simulation and can be combined with parts generated by solid modeling. Finally, aerial image simulation was added, which leads to a very close correspondence of the geometry models with the fabricated structures.

As already indicated, resist development realized by chemical wet etching is closely related to lithography techniques. The following chapter demonstrates how the structuring element algorithm is applied to the simulation of resist development. Additionally some basic aspects concerning the profile evolution will be addressed by means of prototypical benchmark examples.

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