6.1 Thermal Investigations

To account for thermal effects is one of the key requirements for simulation tools since the thermal limit is one of two principal limitations. For (electro-)thermal HEMT simulations proper thermal boundary conditions provided by chip design have to be numerically used. As was shown by Marsetz in [169], the three-dimensional nature of heat flow and chip like thermal boundary conditions have to be accounted for. There is a significant interaction of the single gate-fingers within transistors on chip. In [169] simulations were performed based on a three-dimensional solver by Kawashima [144], further simulations are performed in this work using the three-dimensional simulator SOLIDIS  [135]. Two results are crucial for the determination of the boundary conditions as shown in Fig. 6.1. First, the transition from heat spreading to laminar heat flux towards the substrate only occurs at distances of about 150 $\mu$m from the principal heat sources, the high field region near the gates. Second, in lateral direction a typical pitch of 30-50 $\mu$m to the next gate finger is found. This strongly influences the temperature ${\it T}_\mathrm{L}$ at the observed gate-finger. Third, a typical HEMT area considered for two-dimensional device simulation covers an area of 2-4 $\mu$m$^2$ for the reason of computational efficiency in contrast to the cross-section 400 $\mu$m$\times$500 $\mu$m at least considered for three-dimensional thermal simulation. Thus, the applied boundary conditions for the two-dimensional electro-thermal simulations are just fit conditions and need to be controlled by more complete three-dimensional thermal simulations.

Figure 6.1: Typical dimensions for 3D thermal chip and 2D electro-thermal device simulations.

Fig. 6.2 shows the simulated mid-channel temperatures obtained by two-dimensional electro-thermal simulation, where the substrate thermal resistance is fitted to match the temperatures obtained by three-dimensional simulation.

Figure 6.2: Temperature distribution of a two-dimensional simulation for an on-wafer situation fitted to the boundaries obtained by three-dimensional simulation.

Figure 6.3: Output characteristics with the gate width as a parameter for devices from the same cell on the same wafer.

In Fig. 6.3 a comparison for two devices from the same cell on the same wafer can be observed that differ by the gate width by a factor of 6 and by the single finger width by a factor of 1.5. For low ${\it V}_{\mathrm{GS}}$ the device with the smaller single finger gate width has less ${\mit g}_{\mathrm{m}}$, while for higher ${\it V}_{\mathrm{GS}}$ close to the maximum of ${\it V}_{\mathrm{GS}}$= 1 V a thermal effect becomes visible: the different slope of the output conductance for different gate width can be observed due to the stronger heat dissipation/mm gate width. The output conductance of the bigger device even appears slightly negative for ${\it V}_{\mathrm{GS}}$ where the slope is still positive for the smaller device. Due to the higher power density in the device the thermal effects are more pronounced for the HEMT with the absolute higher gate width. The statistical issues for devices from the same wafer were addressed in Chapter 5.

For GaN HEMTs the thermal management is even more important as the thermal limit is reached before the electrical limit due to the high breakdown voltages relative to e.g. GaAs based HEMTs.

Figure 6.4: Transistor-transistor interaction: image of the transistor test structure.

Figure 6.5: $f_T$ as a function of dissipated power for the test structure.

As we see from three-dimensional simulations, the macroscopic outer periphery, i.e. HEMT mounting and available heat sinks, have a strong impact on the temperatures.

From a microscopic perspective, in [282] it was shown that for the small dimensions prevailing in HEMT heterostructures locally the thermal conductivity is reduced: The small dimensions of the heat sources do not ensure thermal equilibrium of the phonon system required for the solution of the lattice heat flow equation. The extension of the characteristic length of the phonon-phonon interaction amounts to 300 nm in Si at room temperature. The heat source is typically defined by the high field region with extensions of 50 nm.

Another important impact on the boundary conditions for the single transistor fingers is due to the interaction of various transistors on a chip. For this reason a test structure was designed and processed to investigate the interaction for a typical output stage of a high-power amplifier. Fig. 6.4 shows an image of this test structure, which consists of five equal 8$\times$125 $\mu$m HEMTs of ${\it l}_{\mathrm{g}}$= 300 nm. For given thermal boundary conditions, i.e., in this case on-wafer measurements, it is possible to measure the influence the device quantities and reliability. Fig. 6.5 shows the ${\it f}_\mathrm{T}$ values of the innermost transistor as a function of the sum of the dissipated DC power in the whole test structure. The dissipated power is changed by symmetrically switching on additional HEMTs on the test structure. The influence of the distance of the transistors towards the device under test can be estimated from the two values given at the same value of ${\it f}_\mathrm{T}$ for the same dissipated power. The higher ${\it f}_\mathrm{T}$ value corresponds to the outer HEMTs switch on and heating, while the lower value corresponds to the measurements taken for the inner two transistors switched on. Parameters in the investigation are the ${\it V}_{\mathrm{DS}}$ voltage of the innermost transistor, while the other four are always biased at ${\it V}_{\mathrm{DS}}$= 5 V, if switched on. The second parameter is the substrate temperature which was defined by a thermal chuck. Fig. 6.5 demonstrates that the distance of the heat source has a visible effect, especially when the transistor is in thermal compression at high temperatures. Fig. 6.6 shows the impact of the parallel HEMTs on the transconductance ${\mit g}_{\mathrm{m}}$ of the innermost transistor. Thus, for the given mounting configuration of the wafer it is possible to investigate the device as a function of total power dissipation and as a function of the distance of the power source for a given technology, as shown in Fig. 6.5. The reduction of the current gain is relatively more significant for small ${\it V}_{\mathrm{DS}}$, while at higher ${\it V}_{\mathrm{DS}}$ there are saturation effects visible to the decrease of ${\it f}_\mathrm{T}$. Such a concept can help to judge thermal effects without performing a complete thermal analysis of the chip. Fig. 6.7 shows the dependence of the DC output characteristics on the ${\it V}_{\mathrm{DS}}$ pulse-width, when in pulsed operation. The repetition of the ${\it V}_{\mathrm{DS}}$ bias was set to 100 ms. The pulse width was varied down to 500 ns. Fig. 6.7 suggests that pulsed operation requires measurement equipment with pulse lengths of 500 ns and below to avoid thermalization.

Figure 6.6: Transistor-transistor interaction: $g_m$ at $T_{sub}$= 373 K for an 8$\times$125 $\mu$m HEMT as a function of $V_{GS}$ for transistors of the same kind switched in parallel.

Figure 6.7: Pulsed DC-measurements as a function of on pulse width for a repetition rate of 100 ms.