6.4.3 Technology D: Pseudomorphic HEMT on GaAs

For high-power radar and Local Multipoint Distribution Services (LMDS) applications at 35 GHz, another HEMT structure is investigated. Fig. 6.24 shows the power characteristics for a ${\it W}_{\mathrm{g}}$= 8$\times$60 $\mu$m pseudomorphic HEMT at f= 35 GHz. An extremely high power density of 707 mW/mm and an absolute output power ${\it P}_{\mathrm{sat}}$= 340 mW is observed. This value of ${\it P}_{\mathrm{sat}}$ is close to the theoretical limit of ${\it P}_{\mathrm{sat}}$= 800 mW/mm on device level normally considered for pseudomorphic HEMTs assuming realistic matching losses in state-of-the-art circuits [195]. The power capabilities are demonstrated for a device of ${\it W}_{\mathrm{g}}$= 480 $\mu$m overall gate width which is a clear indication for scalable output power up to a gate width of 480 $\mu$m for the single transistor.

Figure 6.24: Output power, gain, and PAE for a 8$\times$60 $\mu$m at f= 35 GHz of Technology D.

Figure 6.25: Load-pull measurements for the same device at f= 40 GHz.

Since an active load-pull system does not provide a stable load for all input power levels, these measurements were performed with a load obtained near $P_{-1dB}$. When tuning the device in the linear range, 10 dB gain are obtained instead of the 8 dB reported in Fig. 6.24. Fig. 6.25 shows the same curves measured at f= 40 GHz for the same bias tuned for maximum ${\it P}_{\mathrm{sat}}$.

Fig. 6.26 and Fig. 6.27 show the impact of the substrate temperature on output power and gain and on the optimum device load, a parameter fundamental to control for high-power amplifier design, especially for different temperatures and gate-widths. For the HEMT measured from Technology D an increase of the magnitude and a decrease of the phase of the load was observed as a function of rising temperature.

Figure 6.26: Saturated output power $P_{sat}$ and gain for f= 35 GHz for two different substrate temperatures $T_{sub}$.

Figure 6.27: Temperature dependence of the optimum load for a substrate temperature $T_{sub}$= 298 K and 353 K.

Figure 6.28: Saturated output power, gain, and PAE of a

Figure 6.29: Saturated output power $P_{sat}$ versus frequency, measured for Technology D for a second HEMT layout.

To control the impact of a non-symmetrical recess in the frequency range of 35 GHz, Fig. 6.28 shows a comparison of the saturated output power for different outer recess lengths ${\it l}_{\mathrm{DR}}$. For each geometry, the ${\it V}_{\mathrm{DS}}$ voltage was optimized in order to make use of the increased breakdown voltage. However, no advantage is found using an extended recess at the frequency of f= 35 GHz from the perspective of saturated output power, on the opposite, the device with the smallest recess length has the highest output power. For the smallest recess length an output power of ${\it P}_{\mathrm{sat}}$= 735 mW/mm for a ${\it W}_{\mathrm{g}}$= 8$\times$60 $\mu$m is found, which corresponds to an absolute output power of ${\it P}_{\mathrm{sat}}$= 352 mW/mm. Fig. 6.29 shows the saturated output power as a function of frequency for an 8$\times$60 $\mu$m HEMT between 26.5 GHz and 40 GHz for a different transistor layout. A general decrease of ${\it P}_{\mathrm{sat}}$ as a function of frequency can be observed, further the different layout reduces the output power ${\it P}_{\mathrm{sat}}$ significantly.

The figure also impressively states the usefulness of Technology D for the whole Ka-band. These and the previous measurements show, that the pseudomporphic HEMT is an ideal candidate for high-power applications in this frequency range due to the high product of ${\it f}_\mathrm{T}$$\times$ ${\it l}_{\mathrm{g}}$. Comparing devices with single and double recess, as performed in this study, the frequency range challenges both approaches from different perspectives. The single recess approaches supply sufficient gain for the whole frequency range, however, they cannot be biased for class A operation with ${\it V}_{\mathrm{DS}}$ significantly exceeding 3 V for reliability reasons. Very careful device optimization is required for the double recess approaches, which provide a sufficiently high breakdown voltage for operation at ${\it V}_{\mathrm{DS}}$ = 5 V and beyond, in order to maintain sufficient gain and device speed for operation at ${\it f}$= 40 GHz. As demonstrated this can be achieved when optimizing Technology D. The optimization procedures are described in the next Chapter.