2.4.1 Digital Silicon CMOS

With device scaling in progress according to Moore's Law ourdays CMOS devices at ${\it l}_{\mathrm{g}}$= 130 nm offer very high ${\it f}_\mathrm{T}$ and ${\it f}_\mathrm{max}$ values. This is shown in Fig. 2.10 taken from the 1999 ITRS road map [252] and accomplished without any specific analog optimization. This renders them suitable for mixed-signal analog-digital applications. At the same time, device scaling represents a fundamental problem for the use of CMOS devices in analog applications, since the voltage possibly applicable, see V $_\mathrm {dd}$ in Fig. 2.10, also scales to values not suitable for medium or even high-power design. There are several solutions under development, including the integration of two different Si technologies [117,308]. The necessary combination of two technologies offers chances for III-V components with regard to the analog parts. If power requirements or noise requirements are high III-V solutions are the best choice also in comparison with optimized Si devices. Thus, hybrid flip chip or other mounting technologies are pursued strongly and widen the range of application for III-V devices [169].

Figure 2.10:  $f_{T}$, $f_{max}$, and applied V$_{dd max}$ as a function of CMOS effective gate length according to ITRS 99 roadmap [252].

Figure 2.11: Reported output power versus frequency for several analog Si technologies.

For analog high power applications, especially up to 2.2 GHz, laterally diffused MOSFETs (LDMOS) are optimized to yield increased breakdown voltage, higher power and PAE, and increased linearity in comparison with typical Si transistors for digital applications. Some output power capabilities reported of this Si MOSFET technology versus frequency are shown in Fig. 2.11.  For extremely high-power RF applications below 1 GHz, SiC based devices were derived from devices developed for high-power switching applications. An overview of such SiC MESFETs can be found in [10].