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4.4 Simulation of a Surface-Channel Charge-Coupled Device

As an example a three-phase, n-channel SCCD composed of fifteen gates has been simulated. The geometry of the device is shown in Fig. 4.11.

The source and drain contacts were held constant at 0 V, the bulk contact at -1 V. The input voltages applied to the gates varied between -1 V in the `off'-state and +5 V in the `on'-state. Fig. 4.12 shows the input signals during $ \mu$s. 180 instances were used to specify 10 periods of the input signals.

Figure 4.11: Geometry of the simulated three-phase, n-channel SCCD.
\begin{figure}
\begin{center}
\includegraphics[width=15cm]{eps/ccdgeometry.eps}\end{center}\end{figure}

Figure 4.12: Clock voltages during the first two clock periods.
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\begin{center}
\resizebox{14cm}{!}{
\psfrag{t [us]}{$\mathsf{t\ [...
...age\ [V]}$}
\includegraphics[width=14cm]{eps/clock.eps}}\end{center}\end{figure}

For spatial discretization of the semiconductor equations a rectangular grid consisting of approximately 8200 points was used.

The simulation was performed on a DEC 7000/640 workstation and required approximately 6 h of CPU time. Ten clock periods were simulated which required approximately 1500 time steps.

Figure 4.13: Electron concentration in the channel region at t = 17.47 . 10-6 s.
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\includegraphics[width=9.5cm,angle=90]{eps/charge1.col.ps}\end{center}\end{figure}

Figure 4.14: Electron concentration in the channel region at t = 17.54 . 10-6 s.
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\includegraphics[width=9.5cm,angle=90]{eps/charge2.col.ps}\end{center}\end{figure}

Fig. 4.13 shows a snapshot of the electron concentration in the channel region at the simulation time t = 17.47 $ \mu$s. The voltage applied to clock  1 and to clock  3 is -1 V, clock  2 is at +5 V. In this picture the accumulation under the `on'-gates and the strong inversion beneath the `off'-gates can be seen.

70 ns later the voltage of clock  3 has been raised to +0.9 V and charge has been transferred and is accumulating under the gates connected to clock  3 as can be seen from Fig. 4.14.

As a further result of the simulation the charge that passed through the source, drain, and bulk contact is plotted in Fig. 4.15. Current flowing into the device is counted positive.

Figure 4.15: Charge transferred through the source, drain, and bulk contact of the simulated CCD during 10 clock periods. Current flowing into the device is counted positive.
\begin{figure}
\begin{center}
\resizebox{14cm}{!}{
\psfrag{t [us]}{$\mathsf{t\ [...
...u As/m]}$}
\includegraphics[width=14cm]{eps/charge.eps}}\end{center}\end{figure}

From Fig. 4.15 it can be seen that during each clock period more electrons are transferred into the device through the source contact than out of the device. At the drain contact the net transferred charge during the first five periods is zero. After five clock periods when the first charge packet reaches the drain the same amount of electrons which enters the device at the source contact leaves the device at the drain contact as can be seen from the identical slopes of the corresponding curves in Fig. 4.15. During the first clock period a considerable amount of electrons flows into the device through the bulk contact. After approximately four clock periods the current through the bulk contact reaches its steady state value and oscillates with three times the clock frequency around an average value.

In this simulation all generation and recombination mechanisms were neglected. Therefore all electrons flowing into the device at the source contact have leave the device at the drain contact. Recombination would cause a reduction of the signal charge when the signal charge density beneath a contact is higher than in equilibrium. Thermal generation on the other hand would cause an increase for charge packets for which the electron concentration is lower than the intrinsic concentration and cause the so-called dark current.


next up previous
Next: 5. Optimization of the Up: 4. Two-Dimensional Transient Simulation Previous: 4.3.3 Interpolation of Sampled
Martin Rottinger
1999-05-31