5.3.3 Device Simulation

For each device two series of device simulations were performed to calculate the on-resistance and the maximum electric field.

The on-resistance was computed from the results of simulations in which the source and gate voltages were held constant at 0 V and 10 V, respectively. The drain voltage was varied from 0 V to 5 V in 0.1 V steps. The ratio of the drain-source voltage and the resulting drain current was multiplied by the number of devices in the packaged transistor and by a calibration factor. Fig. 5.10 shows a plot of the resulting on-resistance. For the optimized device the on-resistance is approximately 20% lower than for the standard device and shows a smaller dependence on the drain current.

Figure 5.10: On-resistance of the optimized device.

Figure 5.11: Maximum electric field of the optimized device.

To determine the maximum electric field in the device the gate voltage was held constant at 0 V and the drain-source voltage was increased from 0 V to 150 V in steps of 5 V. From each simulation step result the maximum magnitude of the electric field was extracted. The result of these simulations is plotted in Fig. 5.11. The maximum of the electric field in the optimized device does not show a linear increase with increasing drain-source voltage as for the standard device. For low drain-source voltages there is a steep increase in the maximum of the electric field. For drain-source voltages higher than approximately 50 V the maximum of the electric field increases slower. The maximum of the electric field is higher for the optimized device for nearly the whole range of simulated drain-source voltages. For drain-source voltage higher than approximately 145 V the maximum electric field in the conventional device is higher than in the optimized device.