1.3 Interconnect Technologies

The vertical electrical interconnections can be created in several ways and at different stages of the fabrication process flow to make 3D integration a reality. In the following sections, descriptions of two important classes of 3D interconnect technologies used at the wafer and/or package fabrication level will be described. Starting from the bottom-most layer, a particular interest comes from the TSV structure, which is used for 3D-SIC and 3D-WLP technologies and represents the most common and successful interconnect approach for 3D integration. TSV design is at the heart of 3D integration and has gained much attention over the last decades in industrial application in the field of electronics, optoelectronics, medical systems, sensor, MEMS, etc. [115]. By following the metallization stacking process until the packaging level, flip-chip solder bumps offer better opportunities as peripheral vertical interconnects between dies or packages to overcome the constraints of wire bonding [122]. Recently, the demand on the 3D integration to use a combination of TSVs and micro-bumps has been increased to obtain better electrical performance and smaller form factors even at the wafer level [141].