1.3.3 Reliability Issues

Although 3D interconnect technologies show distinct advantages and their manufacturing process has almost reached the status of mass production, there are several reliability concerns, as is often the case in emerging technology. Failures in interconnects are the result of the continued increase in interconnect density in the 3D integration design and the necessity of more intense device operative conditions due to the ongoing miniaturization. Reliability issues in interconnects are related to the changes of material properties of metals and dielectrics, such as metal resistivity and dielectric permittivity, beyond critical values, which prevent the intended functions of the ICs, leading to wear-out and defect-related problems. Both metal and dielectric layers play an important role in the reliability of the interconnect system [84]. Metal reliability is typically evaluated by investigating the electrical properties of the material which affect the current density that the metal can carry and, consequently, the resistance of the entire interconnect system. The resulting wear-out failure mechanisms, which occur under the operation of the device, are electromigration and stress induced degradation. As already discussed in Section 1.1.3, the importance of introducing low- dielectric materials increases with reduced dimension and material scaling, which influences the reliability of the interconnect causing defect-related problems, such as leakage and dielectric breakdown. The general issue of low- materials is that they are generally soft and weakly bonded to the silicon or metal lines [6]. The poor adhesion between the metal and the dielectric material results in the development of mechanical stress at their interface.

All 3D interconnect structures described in the previous sections have their specific reliability issues. In TSV-based integrations, reliability concerns are typically identified at the interface of the TSV and at the adjacent metallization levels [61], while electromigration induces voiding at the contact window on the chip side in solder bumps with UBM layer [26]. The main reliability issues in such 3D interconnect structures can be summarized in three categories:

• Stress related degradation: mechanical stress effects which result in local failures affecting the stability and performance of the interconnect system. Several reliability studies [24,61,95] recognize different local wear-out phenomena in interconnects related to thermo-mechanical issues, such as delamination and cracking at the TSV interface or inside solder bumps. Furthermore, the variation of the mechanical strength of the chip, which depends on the design of the interconnect arrays, can cause reliability concerns in the system, such as crack propagation and changes in the mobility of carriers [26].
• Electromigration related failure: it is a wear-out and failure mechanism which is typically related to the high current density which flows in a metal interconnect [84]. Electromigration is a key aspect of interconnect reliability assessment. It is described as the biased motion of atoms towards the anode or cathode of metal lines [46]. A characteristic of electromigration wear-out mechanism is that it causes failure by inducing the nucleation of voids in the metal line. Voids nucleate in the interconnect due to the development of tensile stress, particularly at those locations where the adhesion between the metal layer and the surrounding material is weak [63]. For TSV-based integrations, these sites are observed close to the metallization barrier between the TSV and the adjacent metal RDL [61]. Electromigration behavior in flip-chip solder bumps is expected to be different. During electromigration, an intermetallic compound (IMC) is formed due to the current-induced stress [110,111] the nucleation of a void due to the induced stress may occur at the interface between the bump and the IMC [84].
• Heat transfer related degradation: the components of a chip which generate heat are solder bumps, contact metallization, metal interconnects, and transistors. Heat generation increases with the number of chips in the 3D stack and heat dissipation is a challenging issue. Heat degradation mechanism is a consequence of the multiple effect of the increased temperature during electromigration- and stress-induced degradation processes. On one hand side, the effect of an increased temperature gradient in a 3D design intensifies the material transport by increasing diffusion coefficients; on the other hand side, it activates dislocation movements resulting in plastic effects in the metal interconnects [26]. It is clear that heat transfer problems must be addressed to electromigration and stress-related issues.

Electromigration and stress-induced wear-out phenomena, which affect the interconnect reliability, act together leading to changes in the electrical characteristics of the materials composing the interconnect structure [26]. Since the physics behind the electromigration phenomenon is well understood, it can be employed to the comprehension of the electromigration failure mechanisms in 3D integration technologies. Furthermore, it can provide a stronger basis for design of reliable interconnects and contributes for explaining experimental observations. Therefore, design engineers need to be aware of the active wear-out failure mechanisms which result from electromigration phenomenon. Electromigration becomes a limiting factor for high current density flow in interconnects and reduces the lifetime of the technology. The identification of failure modes and the prediction of reliability limits related to electromigration are therefore a crucial necessity in 3D integration. The electromigration phenomenon will be dealt with in more detail in the following section.