List of Figures

• 1.1. Basic steps of the FEOL fabrication process.
• 1.2. Basic steps of the BEOL fabrication process.
• 1.3. The half pitch of the first metallization layer is the defining feature for chips. The gate width represents the smallest feature.
• 1.4. Conceptual view of the space transformation of (a) 2D planar SoC to (b) 3D-SoC.
• 1.5. Classification of interconnects.
• 1.6. Schematic representations of the main 3D integration approaches: (a) 3D-IC, (b) 3D-SIC, (c) 3D-WLP, and (d) 3D-P.
• 1.7. 3D view of a TSV structure.
• 1.8. Cross section view of an open TSV structure.
• 1.9. (a) Example of 3D integration with solder bumps. (b) Zoomed-in detailed profile view of a solder bump.
• 1.10. Typical electromigration resistance change with time for a given interconnect. Two electromigration failure phases are shown.
• 1.11. Time to failure dependence on current density illustrates the behavior of equation 1.2 for a constant test temperature. The line indicates the fitting to the data from which the determination of the current density exponent is obtained from its angular coefficient.
• 1.12. Main diffusion paths in a passivated interconnect structure: a) bulk, b) grain boundary, and c) material interface.
• 2.1. The two contributions of the electromigration driving force.
• 2.2. Stress build-up due to vacancy accumulation and depletion in a passivated metal line. Tensile stresses lead to void formation.
• 2.3. The time evolution of the stress build-up in a semi-infinite line at x=0.
• 2.4. Schematic of the embryo at the line/passivation interface.
• 2.5. Sharp (a) and diffuse (b) description of the void interface.
• 3.2. Grain boundary of width δ embedded in a bulk. The fluxes J_v¹ and J_v² change the concentration of the mobile vacancies (C_v¹ and C_v²) and immobile vacancies (C_v^t). Vacancies are trapped into the grain boundary with trapping rate ω_t and released to the grains with release rate ω_r.
• 3.3. Schematic representation of an interface of width δ between two materials. The flux J_v¹ changes the concentration of the mobile vacancies (C_v¹) and immobile vacancies (C_v^t). Vacancies are trapped into the material interface with trapping rate ω_t and released to the bulk with release rate ω_r.
• 3.4. Time evolution of the stress build-up due to electromigration in a copper interconnect. Two different threshold tensile stresses for differing patch radii R_p are presented.
• 3.5. Idealization of the void surface in a 2D conducting interconnect line.
• 3.6. Order parameter distribution in a 2D conducting metal line.
• 3.7. Quartic double well potential for the free energy function.
• 3.8. Evolution of an elliptical void in a non-electrically conducting line. The ellipse collapses into a circle due to surface energy driven diffusion.
• 3.9. Order parameter distribution of an evolving stable circular void in an interconnect line under electrical loading ΔV_e. The void profiles are plotted at (a) t = 0s, (b) t = 1s, (c) t = 2s, and (d) t = 20s. The void maintains its circular shape as it migrates through the line due to a combination of the surface energy gradient and the electromigration force.
• 3.10. Migration velocity v_n as a function of electrical potential gradient for different void radii r_v. The lines indicate the fit according to equation (3.89).
• 3.11. Schematic cross section view of a conducting metal line with an initial small void of radius r_v.
• 4.1. Schematic view of the linear discretization of the domain in elements and nodes. The true solution is represented as a continuous function (dotted line) and the approximate solution is described as a piecewise polynomial (solid line).
• 4.2. Schematic view of the finite element mesh of the domain Ω=(0,L), with the definition of the boundary conditions at the endpoints.
• 4.3. Schematic view of the linear finite element approximation. The true solution φ(x) (dotted line) and the construction of the approximate solution φ_h¹ (solid line), within the element Ω₁, are presented.
• 4.4. Schematic view of the assembly of two linear elements Ω₁ and Ω₂. The definition of the boundary conditions at the endpoints, the balance of the unknown source terms, and the continuity of the solution at node 2 are presented..
• 4.5. Basic steps to perform a finite element analysis in COMSOL Multiphysics^®.
• 4.6. Flow chart of the full procedure for electromigration simulation in COMSOL Multiphysics^®. The two phases of the electromigration problem, void nucleation and void evolution, are presented..
• 4.7. Order parameter distribution in an interconnect line. Different mesh densities employed in the numerical calculations are shown. The coarse mesh density used to calculate the voltage distribution through the bulk is refined for the computation of the order parameter along the metal-void interface. The inset zoom shows the details of the mesh density at the interface thickness.
• 5.1. Diagonal cut-through profile view of the analyzed open copper TSV structure. The upper part of the interconnect layout is known as TSV top while the lower side is the TSV bottom. The TSV aspect ratio is 2.5:1 (TSV height / TSV diameter). The zoomed-in detail view of the TSV bottom depicts the front side layers stack. The arrow shows the direction of the electron flow..
• 5.2. Maximum relative vacancy concentration change over time in the simulated structure. The cross section views show the relative vacancy concentration distribution at the TSV bottom during the three phases of vacancy dynamics. The peak values are located close to the copper/titanium nitride (metal/barrier) interface.
• 5.3. Profile view of the mechanical stress (MPa) distribution at the open copper TSV bottom after 10000 hours of current flow. The maximum tensile stresses are located at the Cu/TiN/SiO₂ intersection.
• 5.4. Evolution of the maximum tensile stress in the analyzed structure for different applied current densities. The electromigration void nucleation times t_e obtained for each curve profile are shown in the x-axis.
• 5.5. (a) General cross section view of a through silicon via. The portion of the structure with the initial void under consideration for simulation is highlighted. (b) The cross-sectional view of the considered 2D domain Ω with the applied boundary conditions.
• 5.6. Order parameter distribution of the evolving void at the bottom of the TSV structure presented in (5.5(a)). (a) A small initial void is placed within the structure. (b) After 500h, it begins to move in the direction of the electron flow. (c) Following this phase, vacancies tend to accumulate at the void surface whereby it grows further. (d) Due to an increase in the distribution of the current density along the void surface, void propagation accelerates triggering open circuit failure.
• 5.7. Current density dependence on the void radius for the initial applied electrical loading j₀. Cross section views of the current density distribution are shown at two different void radii r_v: a) 10nm and b) 6μm. Current crowding increases as soon as the void becomes larger. The distribution of the average current density over the void surface is represented by the arrows.
• 5.8. Interconnect resistance change as a function of time for different applied electrical loadings obtained by following (a) the diffuse interface method and (b) a semi-empirical approach. The failure criterion is a 20% increase in resistance. The electromigration void evolution times t_e obtained for each curve profile are shown on the x-axis.
• 5.9. Complete electromigration resistance trace profile for the initial applied current density j₀ by following the two methodologies describing the void growth. The two phases of failure are shown..
• 5.10. TTF depends on the current density. The line indicates the fit according to Black's equation and the current density exponent n is its angular coefficient.
• 5.11. Profile view of the solder bump geometry used for simulations. On the top of the Sn bump, a Ni UBM layer is placed. The arrow shows the direction of the electron flow.
• 5.12. Profile view of the mechanical stress (MPa) distribution in the solder bump geometry after 14 hours of current flow. The maximum tensile stress is located at the top of the Sn bump beneath the Ni UBM layer.
• 5.13. Profile view of the current density (MA/cm²) distribution in the solder bump geometry after 14 hours of current flow. Current crowding is observed close to the top of the Sn bump beneath the Ni UBM layer.
• 5.14. Time evolution of the maximum tensile stress in the analyzed structure for six applied current densities. The threshold stress σ_thr for void nucleation is shown in the x-axis.
• 5.15. TTF depends on the current density. The solid line indicates the fit according to the compact model for lifetime prediction presented in equation (5.3).
• 5.16. Schematic view of the (a) linear and (b) L-shaped geometry used in this analysis. The zoomed-in detail view of a triple point depicts the mesh density employed in the numerical calculations. The arrows show the direction of the current density. The red circles S₁ and S₂ represent the spots where peak values of vacancy concentration and stress are extracted.
• 5.17. Current density dependence on arc radius r_a. Cross section views of the current density distribution are shown for two different arc radii r_a: a) 0μm and b) 0.25μm. Current crowding decreases as soon as the arc radius increases.
• 5.18. Maximum relative vacancy concentration change over time in the simulated structures. The peak values of vacancy concentration are extracted at the geometrical ends and at the triple points for both cases.
• 5.19. Time evolution of the maximum tensile stress in the analyzed structures. The peak values of tensile stress are extracted at the geometrical ends and at the triple points for both cases. The cross section view shows the hydrostatic stress distribution (MPa) in the region close to the triple point after 2.5 hours. The peak values of tensile stress are located inside the triple point.