A.2.3.4 Cascade Voltage Switch Logic

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A.2.3.4 Cascade Voltage Switch Logic

Cascade voltage switch logic (CVSL) belongs to class of differential-logic types. The idea is to use a dual n-block instead of a dual p-block and a pair of cross-coupled PMOS transistors compute the logic function and its complement. CVSL can be roughly as fast as dynamic logic,^A.4 it dissipates almost as little static power as static CMOS and is relatively robust against large $\ensuremath{I_{\mathit{off}}}$ . Also, as a consequence of the differential signals, which means an effective doubling of the voltage swing, CVSL is very robust against noise and against capacitive noise coupling. On the other hand, the overhead is considerable: twice the transistor count of dynamic logic and pseudo-NMOS, and twice the dynamic power consumption. Nevertheless, CVSL is a good candidate for low-voltage applications, also in combination with other types of logic.

Footnotes

... logic,^A.4: There seems to be some disagreement on the speed of CVSL (compare, e.g., [36,41,42]), which indicates that the dimensioning of the PMOS pair is critical.

G. Schrom