Most popular textbooks on semiconductor physics or VLSI technology
describe the MOSFET primarily in the strong-inversion regime,
whereas the subthreshold region is treated as an essentially
spurious phenomenon [77,78,89,26,87,28].
The equations given for the subthreshold drain current are either
not suitable for practical use (for circuit design)
as they are either implicit or they contain some other unknowns
like the surface-potential displacement
[78,89,26],
or, they are empirical equations in the form
,
where
is to be determined experimentally or fitted as a model
parameter [28,42,86,68].
Some authors mention the effect but give no equation [87].
Furthermore, some textbooks on VLSI design develop a mathematical
framework based on the assumption that the subthreshold current
is exactly zero or at least negligible [26,87].
In addition, CMOS circuits are usually treated as if they were ratioless
(cf. Section A.2.1),
which is true only if the off-state current is negligible.
The low attention paid to this phenomenon is partly understandable
from the fact that in the traditional processes (
)
threshold voltage has been quite high (600...800mV), so that the
off-state current was indeed almost negligible
Clearly, a full incorporation of the subthreshold current into the mathematical framework used for circuit design is almost impossible, regarding its derivation, teaching, and practical application. However, the lack of proper theoretical and numerical treatment of this phenomenon has lead to unrealistically and uneconomically low leakage constraints which were adhered to, partly, because they had worked in the past and the effect of increased leakage on circuit functionality was not widely known, and also because the calculation of the standby power consumption usually did not consider any architectural or circuit-style options (cf. Section 3.2.2.1).