2.9 ULP Leverage

Compared to conventional CMOS technologies Ultra-Low-Power CMOS features a series of substantial advantages. Some of the strategies of Ultra-Low-Power CMOS are being adopted for novel deep-submicron technologies.

• Reduced power consumption and thus also reduced thermal power dissipation result from the lower supply voltage.

• The impact of velocity saturation is reduced by a lower supply voltage for a given gate length.

• The effective mobility degradation by the transversal field in the channel is reduced by the lower supply voltage.

• The latch-up problem is eliminated by a reduction of the supply voltage to below 1.5V (assuming conventional well routing [41]).

• Electromigration problems are reduced as a consequence of the lower currents in moderate-performance ULP technologies.

• Drain-induced barrier lowering (DIBL) is reduced to some extent by the lower supply voltage, which allows more freedom in the design of the channel profile.

• The effect of gate-induced drain leakage (GIDL) is eliminated because of the lower supply voltage and higher source/drain doping.

• Hot-carrier degradation problems in the channel are virtually eliminated as the number of high-energetic electrons is much lower due to the lower supply voltage and injected hot electrons can tunnel out of the oxide again because of the thin gate oxide.

• Time-dependent dielectric breakdown (TDDB) is retarded as the lower supply voltage reduces the electric field in the gate oxide. Furthermore, the oxide can be made thinner, which results in thigher oxide reliability.

• Improved process scalability results from the high level of leakage currents which allows to achieve a higher drive current.

• Reduced process cost is a consequence of the lower complexity of moderate-performance ULP technologies.

• Better exploitation of a wider range of power sources is enabled by the lower supply voltage.