2. The Ultra-Low-Power Approach

The main part of the power consumption of integrated circuits is the dynamic component which is a square function of the supply voltage $\ensuremath{P_{\mathit{dyn}}}\xspace \propto \ensuremath{V_{\mathit{DD}}}\xspace ^2 C$. Therefore, one natural way to reduce the power consumption is to decrease the supply voltage, which also improves device reliability. This has lead to the so-called Low-Power technologies, which operate at $\ensuremath{V_{\mathit{DD}}}\xspace = \mathrm{3.3V\,and\,2.5V}$. However, these supply levels are still quite high, and the potential power savings are not fully exploited yet.

The primary concept of Ultra-Low-Power (ULP) technology is to reduce the supply voltage and the threshold voltages to such small values, that the total power consumption approaches a minimum while the required device performance is maintained. The reduced threshold voltage results in an increased leakage current which is still acceptable with regard to power efficiency and circuit functionality. When the voltages are so small that the device performance starts to degrade the system's performance could still be maintained by employing pipelined or parallel architectures. This enables a reduction of the power consumption by orders of magnitude compared to conventional CMOS operating at large supply voltage and low leakage.

Furthermore, as the minimum feature size enters the deep-sub-micron regime, the relative performance loss due to the supply voltage reduction is smaller. This is owing to various physical effects, such as velocity saturation and mobility degradation, which are less severe at low voltages. Other degradation effects, such as GIDL (gate induced drain leakage), hot-carrier degradation, or latch-up are greatly reduced or even eliminated. This provides an extended scalability of existing CMOS technologies.