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2.1 Digital-Circuit Speed and Power Consumption

The essential figures of merit of a digital circuit or system are speed and power consumption. The usual measure for speed is a (reciprocal) delay time $\ensuremath{t_{\mathit{d}}}$ or a maximum clock frequency $\ensuremath{f_{\mathit{c,max}}}$ . Power efficiency can be determined as the total power $\ensuremath{P_{\mathit{tot}}}$ or in terms of a switching energy $\ensuremath{E_{\mathit{s}}}$ , i.e., the average energy consumed for one switching transition of a device. Precise definitions and methods for measuring or computing these figures of merit are given in Chapter 3 together with a basic introduction to VLSI circuits and technology in Appendix A. For the purpose of this section, i.e., to develop the foundation for Ultra-Low-Power technologies, we will use a set of simpler equations which are accurate enough to reflect the fundamental relations between the digital system and the operating conditions on the one hand, and speed and power consumption on the other hand.

For the following, we will consider a digital circuit as a network of switches with parasitic capacitances, which can be described statistically in terms of average values (for more background information refer to Sections A.2 and A.3). Thus, we examine one representative pair switches that charge and discharge a representative load capacitance $\ensuremath{C_{\mathit{L}}}$ to the supply voltage $\ensuremath{V_{\mathit{DD}}}$ with a current $\ensuremath{I_{\mathit{on}}}$ . Each switch in the off-state draws a leakage current $\ensuremath{I_{\mathit{off}}}$ . For simplicity, any short-circuit current flowing across the switches is assumed to be negligible (which is usually acceptable), and a pair of switches is regarded as one device.

The total power consumption per device is the sum of a dynamic component from charging and discharging the capacitance and a static component from the leakage current:

$\begin{displaymath} \ensuremath{P_{\mathit{tot}}}\xspace = \ensuremath{P_{\math... ...I_{\mathit{off}}}\xspace \ensuremath{V_{\mathit{DD}}}\xspace .\end{displaymath}$

(2.1)

In this expression $\ensuremath{f_{\mathit{c}}}$ is the clock frequency and $\ensuremath{{\mathit{ar}}}$ is the switching probability, the so-called activity ratio. A more universal measure is the switching energy

$\begin{displaymath} \ensuremath{E_{\mathit{s}}}\xspace = \ensuremath{C_{\mathit... ...{I_{\mathit{off}}}\xspace \ensuremath{V_{\mathit{DD}}}\xspace \end{displaymath}$

(2.2)

which is related to the power consumption as

$\begin{displaymath} \ensuremath{P_{\mathit{tot}}}\xspace = \ensuremath{{\mathit... ...th{f_{\mathit{c}}}\xspace \ensuremath{E_{\mathit{s}}}\xspace .\end{displaymath}$

(2.3)

The advantage of using the switching energy rather than the total power consumption is that $\ensuremath{E_{\mathit{s}}}$ is independent of the system throughput. For example, when pipelined architectures are considered the power consumption varies with the architectural changes, but the switching energy does not and is therefore the better candidate to optimize.

The speed of a digital circuit can be characterized in two ways: the delay time $\ensuremath{t_{\mathit{d}}}$ which is assumed as

$\begin{displaymath} \ensuremath{t_{\mathit{d}}}\xspace = {\displaystyle\frac{\e... ...\mathit{DD}}}\xspace }{\ensuremath{I_{\mathit{on}}}\xspace }} ,\end{displaymath}$

(2.4)

and the maximum clock frequency $\ensuremath{f_{\mathit{c,max}}}$ which is given by

$\begin{displaymath} \ensuremath{f_{\mathit{c,max}}}\xspace = {\displaystyle\fra... ...h{t_{\mathit{d}}}\xspace \ensuremath{{\mathit{ld}}}\xspace }} .\end{displaymath}$

(2.5)

In this equation the logic depth $\ensuremath{{\mathit{ld}}}$ is the number of stages through which a switching event must propagate during one clock cycle.

Clearly, a system is most efficient when operated at the maximum clock frequency. Combining (2.2), (2.4), and (2.5) assuming that $\ensuremath{f_{\mathit{c}}}\xspace = \ensuremath{f_{\mathit{c,max}}}\xspace$ yields the following fundamental equation:

$\begin{displaymath} \ensuremath{E_{\mathit{s}}}\xspace = \ensuremath{C_{\mathit... ...off}}}\xspace }{\ensuremath{I_{\mathit{on}}}\xspace }} \right] \end{displaymath}$

(2.6)

Note, that the switching energy is not the same as the commonly quoted power-delay product, but

$\begin{displaymath} \ensuremath{E_{\mathit{s}}}\xspace = \ensuremath{P_{\mathit... ...{{\mathit{ld}}}\xspace }{\ensuremath{{\mathit{ar}}}\xspace }} .\end{displaymath}$

(2.7)

Aside from circuit functionality and speed and assuming $\ensuremath{I_{\mathit{off}}}$ to be essentially constant the following two conclusions can be drawn from (2.6):

1.: The switching energy increases quadratically with the supply voltage.
2.: The leakage current $\ensuremath{I_{\mathit{off}}}$ does not increase the switching energy as long as $\ensuremath{I_{\mathit{off}}}\xspace /\ensuremath{I_{\mathit{on}}}\xspace \ll \ensuremath{{\mathit{ar}}}\xspace /\ensuremath{{\mathit{ld}}}\xspace$ .

Thus, the key to reducing the power consumption is to reduce the supply voltage. Typical values of $\ensuremath{{\mathit{ar}}}\xspace /\ensuremath{{\mathit{ld}}}\xspace$ for a microprocessor are 0.1/7, i.e., the leakage current can be almost as large as $\ensuremath{I_{\mathit{on}}}\xspace /70$ which is several orders of magnitude above the conventional leakage constraints.

Next: 2.2 Characteristic Voltages Up: 2. The Ultra-Low-Power Approach Previous: 2. The Ultra-Low-Power Approach

G. Schrom