Although one of the goals of Ultra-Low-Power CMOS is to maintain portability of existing circuits, this can be achieved only to a limited extent. This is due to the fact that most high-performance digital VLSI systems employ dynamic circuits (such as domino logic) to achieve higher speed and density (cf. Section A.2.3). Unfortunately, dynamic circuits require a small off-state current which sets a lower limit to the threshold voltage. Although dynamic circuits would work down to 500mV supply voltage with high power efficiency, they would not meet the performance requirements. Static logic, on the other hand, is very robust against high leakage currents and can therefore be scaled to much lower voltages than dynamic logic. Unfortunately, static logic consumes more space on a chip than dynamic logic. There are, however, alternatives to pure static or dynamic circuits, which combine the robustness of static logic with the speed and density of dynamic logic. For example, one could use latched dynamic logic, pseudo-NMOS logic (for large-fan-in NOR gates), or cascade voltage switch logic (CVSL) in time-critical signal paths (see Section A.2.3.4).